Frequency Modulated Phase Locked Loop (FMPLL)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
4-13
Preliminary
After the PLL acquires lock after reset, the LOCK and LOCKS status bits are set. If the EPREDIV or
EMFD are changed, or if an unexpected loss-of-lock condition occurs, the LOCK and LOCKS status bits
are negated. While the PLL is in an unlocked condition, the system clocks continue to be sourced from the
PLL as the PLL attempts to re-lock. Consequently, during the re-locking process, the system clock
frequency is not well defined and may exceed the maximum system frequency violating the system clock
timing specifications. Because of this condition, using the loss-of-lock reset function is recommended.
After the PLL has re-locked, the LOCK bit is set. The LOCKS bit remains cleared if the loss of lock was
unexpected. The LOCKS bit is set to one when the loss of lock was caused by changing the EPREDIV or
EMFD fields.
4.4.3.2
Loss-of-Clock Detection
When enabled by the LOCEN bit in the ESYNCR2, the loss-of-clock (LOC) detection circuit monitors the
input clocks to the phase/frequency detector (PFD) (see
). When the reference or feedback clock
frequency falls below a minimum frequency, the LOC circuitry considers the clock to have failed and a
loss-of-clock status is reflected by the sticky LOCF bit, and non-sticky LOC bit in the SYNSR. See
MPC5510 Microcontroller Family Data Sheet
for the minimum clock frequency. In PLL Off mode, the
loss-of-clock circuitry is disabled.
Depending on which clock source has failed, the LOC circuitry switches the PLL’s output clock source to
the remaining operational clock, if enabled by LOCEN. The PLL’s output clocks are derived from the
alternate clock source until reset is asserted. If the reference fails, the PLL goes out of lock and into
self-clocked mode (SCM) (see
). The PLL remains in SCM until the next reset. When the PLL
is operating in SCM, the PLL will run open loop at a default VCO frequency. The RFD will set to
divide-by-4 to ensure the clock presented to the system will be well below the maximum allowable
frequency for the device.
If the loss-of-clock condition is due to a PLL failure (i.e., loss of feedback clock),
the PLL reference becomes the system clocks source until the next reset, even if the PLL regains itself and
re-locks.
A special loss-of-clock condition occurs when both the reference and the PLL fail. The failures may be
simultaneous or the PLL may fail first. In either case, the reference clock failure takes priority and the PLL
attempts to operate in SCM. If successful, the PLL remains in SCM until the next reset. During SCM,
modulation is always disabled. If the PLL cannot operate in SCM, the system remains static until the next
reset. If a loss-of-clock reset is enabled, the reset switches the bus clocks over to the 16 MHz IRC (and
switches off the PLL).
Table 4-12. Loss-of-Clock Summary
Clock Mode
System Clock
Source
before Failure
REFERENCE FAILURE
Alternate Clock Selected by
LOC Circuitry until Reset
PLL FAILURE
Alternate Clock Selected by
LOC Circuitry until Reset
PLL
PLL
PLL self-clocked mode
PLL reference
PLL bypass
Ext. Clock(s)
None
NA
Note: The LOC circuit monitors the inputs to the PFD: reference and feedback clocks (see
).
