Frequency Modulated Phase Locked Loop (FMPLL)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
4-14
Freescale Semiconductor
Preliminary
4.4.3.3
PLL Normal Mode Without FM
In PLL mode, the system clocks are synthesized by the FMPLL by multiplying up the reference clock
frequency. It is critical that the system clock frequency remain within the range for the device (see
MPC5510 Microcontroller Family Data Sheet
). The output of the FMPLL can be divided down in powers
of two up to 128 to reduce the system frequency with the ERFD. The ERFD is not contained in the
feedback loop of the PLL, so changing the ERFD bits does not affect FMPLL operation. Finally, the PLL
can be frequency modulated to reduce electromagnetic interference often associated with clock circuitry.
shows the overall block diagram for the PLL. Each of the major blocks is discussed briefly in
the following sections.
4.4.3.3.1
Phase/Frequency Detector
The phase/frequency detector (PFD) is a dual-latch phase-frequency detector. It compares both the phase
and frequency of the reference clock and the feedback clock. The reference clock comes from the crystal
oscillator or an external clock source. The feedback clock comes from the VCO output divided down by
the EMFD in normal PLL mode.
When the frequency of the feedback clock equals the frequency of the reference clock (i.e. the PLL is
frequency locked), the PFD will pulse the UP or DOWN signals depending on the relative phase of the
two clocks. If the falling edge of the reference clock leads the falling edge of the feedback clock, then the
UP signal is pulsed. If the falling edge of the feedback clock leads the falling edge of the reference clock,
then the DOWN signal is pulsed. The width of these pulses relative to the reference clock is dependent on
how much the two clocks lead or lag each other. After phase lock is achieved, the PFD continues to pulse
the UP and DOWN signals for a very short duration during each reference clock cycle. These short pulses
force the PLL to continually update and prevent a frequency drift phenomena referred to as
“dead-banding.” Dead-band describes the minimum amount of phase error between the reference and
feedback clocks that a phase detector cannot correct.
4.4.3.3.2
Charge Pump/Loop Filter
Operation of the charge pump is controlled by the UP and DOWN signals from the PFD. They control
whether the charge pumps apply or remove charge, respectively, from the loop filter.
4.4.3.3.3
VCO
The voltage into the VCO controls the frequency of its output. The frequency-to-voltage relationship
(VCO gain) is positive.
4.4.3.3.4
EMFD
The MFD divides down the output of the VCO and feeds it back to the PFD. The PFD controls the VCO
frequency (via the charge pump and loop filter) such that the reference and feedback clocks have the same
frequency and phase. Thus, the input to the MFD, which is also the output of the VCO, is at a frequency
that is the reference frequency multiplied by the same amount the MFD divides by. For example, if the
MFD divides the VCO frequency by 48, then the PLL will be frequency locked when the VCO frequency
is 48 times the reference frequency. The presence of the MFD in the loop allows the PLL to perform
frequency multiplication, or synthesis.
