Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
31-64
Freescale Semiconductor
Preliminary
To maximize settling time, when a conversion command is in buffer ENTRY1 and another conversion
command is identified in ENTRY0, then the channel number of ENTRY0 is sent to the
MUX control logic
half an ADC clock before the start of the sampling phase of the command in ENTRY0. This pipelining of
sample and settling phase is shown in
This provides more accurate sampling, which is specially important for applications that require high
conversion speeds, i.e., with the ADC running at maximum clock frequency and with the analog input
voltage sampling time set to a minimum (2 ADC clock cycles). In this case the short sampling time may
not allow the multiplexers to completely settle. The second advantage of pipelining conversion commands
is to provide equal conversion intervals even though the sample time increases on second and subsequent
conversions. See
. This is important for any digital signal process application.
Figure 31-38. On-Chip ADC Control Scheme
MUX
40:1
CFIFOn
ADC0
BIAS
GEN
MUX
Control
Logic
(32-bits)
RFIFOn
(16-bits)
AN0-AN39
REFBYPC
MA0, MA1,
Configuration
Registers
EMUX0
Entry1
LST0
Entry0
ADC0 Buffer
Register Data 0
CHANNEL_NUMBER0
MESSAGE_TAG0;
FMT0, CAL0
Result Format
and
Calibration
Submodule
FIFO
Control
Unit
Result0
Time Stamp0
Time
Stamp
Logic
TBC_CLK_PS
TSR0
ADC0_Result0
ADDR or/and DATA
MA2
Configuration Register Fields
NOTE: n = 0, 1, 2, 3, 4, 5
REF
GEN
Pre
Charge
