Media Local Bus (MLB)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
33-5
Preliminary
33.3.1
Register Descriptions
This section lists the registers and bits that are used to control the SoftMLB Interface Logic.
33.3.1.1
MLB Module Configuration Register (MLB_MCR)
The MLB_MCR contains bits that configure the SoftMLB Interface Logic.
Offset M0x0000
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MDIS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MD
A
T
OBSE
MSIG
OBSE
MSLO
TE
0
0
M
SVRQIE
MD
A
T
RQ
E
0
0
MSVRQDL
M
SVRQCIE
M
IFSEL
MSBFEPOL
MDBFEPOL
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 33-2. MLB Module Configuration Register (MLB_MCR)
Table 33-3. MLB Module Configuration (MLB_MCR) Register Field Descriptions
Field
Description
MDIS
Module Disable. Controls whether the SoftMLB Interface Logic is enabled or not. When MDIS is set, the
SoftMLB Interface logic is asynchronously held in reset and disabled. When disabled, clocks are stopped to
the non-memory mapped logic. Register reads and writes are still accessible. The DSPI_SS is driven high
(DSPI are de-selected). The SoftMLB Interface Logic also masks out all received bits on DSPI_S_OUT and
DSPI_D_OUT. Once this signal is cleared, the SoftMLB Interface Logic requires some time to synchronize to
the MLB Bus. MLB_MSR[MSYSS] = 1 indicates that the logic has synchronized.
0 Enable the SoftMLB Interface Logic
1 Disable the SoftMLB Interface Logic – Default out of reset
bits 1–15
Reserved.
