MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
23-6
Freescale Semiconductor
if V
RC33
leads or lags V
DDSYN
by more than those amounts. The value of that higher spike in current
depends on the board power supply circuitry and the amount of board level capacitance.
When powering down, V
RC33
and V
DDSYN
do not have a delta requirement to each other because the
bypass capacitors internal and external to the SoC already are charged.
When not powering up or down, V
RC33
and V
DDSYN
do not have a delta requirement to each other for the
VRC to operate within specification.
23.5.3.1
Power-Up Sequence If V
RC33
Grounded
In this case, the 1.5 V V
DD
supply must rise to 1.35 V before the 3.3 V V
DDSYN
and the RESET power
supplies rise above 2.0 V. This is to insure that digital logic in the PLL on the 1.5 V supply will not begin
to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V POR is
disabled, the internal 3.3 V POR or the RESET power POR must be depended on to hold the device in
reset. Because they may negate as low as 2.0 V, it is necessary for V
DD
to be within spec before the 3.3 V
POR and the RESET power POR negate.
Figure 23-4. Power-Up Sequence, V
RC33
Grounded
23.5.3.2
Power-Down Sequence If V
RC33
Grounded
In this case, the only requirement is that if V
DD
falls below its operating range, V
DDSYN
or the RESET
power must fall below 2.0V before V
DD
is allowed to rise back into its operating range. This is to insure
that digital 1.5 V logic that is only reset by ORed_POR, which may have been affected by the 1.5 V supply
falling below spec, will be reset properly.
1.35V
2.0V
V
DDSYN
and RESET power
V
DD
NOTE: V
DD
must reach 1.35V before V
DDSYN
and RESET reach 2.0V.
Summary of Contents for MPC5553
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