MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
3-4
Freescale Semiconductor
3.1.3.2
Integer Unit Features
The integer unit supports single cycle execution of most integer instructions:
•
32-bit AU for arithmetic and comparison operations
•
32-bit LU for logical operations
•
32-bit priority encoder for count leading zeros function
•
32-bit single cycle barrel shifter for static shifts and rotates
•
32-bit mask unit for data masking and insertion
•
Divider logic for signed and unsigned divides in 6-16 clocks with minimized execution timing
•
Pipelined 32x32 hardware multiplier array supports 32x32->32 multiply with 3 clock latency, 1
clock throughput
3.1.3.3
Load/Store Unit Features
The load/store unit supports load, store, and the load multiple / store multiple instructions:
•
32-bit effective address adder for data memory address calculations
•
Pipelined operation supports throughput of one load or store operation per cycle
•
Dedicated 64-bit interface to memory supports saving and restoring of up to two registers per cycle
for load multiple and store multiple word instructions
3.1.3.4
MMU Features
The features of the MMU are as follows:
•
Virtual memory support
•
32-bit virtual and physical addresses
•
8-bit process identifier
•
32-entry fully associative TLB
•
Support for nine page sizes (4, 16, 64, and 256 Kbytes, 1, 4, 16, 64, and 256 Mbytes)
•
Entry flush protection
3.1.3.5
L1 Cache Features
The features of the cache are as follows:
•
32-kilobyte, 8-way set associative unified cache in the MPC5554; 8-kilobyte, 2-way set associative
unified cache in the MPC5553.
•
Copyback and writethrough support
•
8-entry store buffer
•
Push buffer
•
Linefill buffer
•
32-bit address bus plus attributes and control
•
Separate unidirectional 64-bit read data bus and 64-bit write data bus
•
Supports cache line locking
•
Supports way allocation
Summary of Contents for MPC5553
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