MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
9-17
9.3.1.8
eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
The EDMA_CEEIR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_EEIRH or EDMA_EEIRL to disable the error interrupt for a given channel. The data value on a
register write causes the corresponding bit in the EDMA_EEIRH or EDMA_EEIRL to be cleared. Setting
bit 1 (CEEI
n
) provides a global clear function, forcing the entire contents of the EDMA_EEIRH or
EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of this register return all
zeroes. For the MPC5553, bit 2 (CEEI1) is not used.
9.3.1.9
eDMA Clear Interrupt Request Register (EDMA_CIRQR)
The EDMA_CIRQR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_IRQRH or EDMA_IRQRL to disable the interrupt request for a given channel. The given value
on a register write causes the corresponding bit in the EDMA_IRQRH or EDMA_IRQRL to be cleared.
Setting bit 1 (CINT
n
) provides a global clear function, forcing the entire contents of the EDMA_IRQRH
or EDMA_IRQRL to be zeroed, disabling all DMA interrupt requests. Reads of this register return all
zeroes. For the MPC5553, bit 2 (CINT1) is not used.
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
CEEI[0:6]
Reset
0
0
0
0
0
0
0
0
Reg Addr
Base + 0x001B
Figure 9-11. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
Table 9-9. EDMA_CEEIR Field Descriptions
Bits
Name
Description
0
—
Reserved.
1–7
CEEI
[0:6]
Clear enable error interrupt
0–63 Clear corresponding bit in EDMA_EEIRH or EDMA_EEIRL
64–127 Clear all bits in EDMA_EEIRH and EDMA_EEIRL
Note: For the MPC5553, the value 32-63 [bit 2 (CEEI1)] is reserved.
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
CINT[0:6]
Reset
0
0
0
0
0
0
0
0
Reg Addr
Base + 0X001C
Figure 9-12. eDMA Clear Interrupt Request (EDMA_CIRQR) Fields
Summary of Contents for MPC5553
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