MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
1-13
1.5
Detailed Features
The following sections provided detailed information about each of the on-chip modules.
1.5.1
e200z6 Core Overview
The MPC5553 and MPC5554 use the e200z6 core explained in detail in the
e200z6 PowerPC
TM
Core
Reference Manual
. The e200z6 CPU utilizes a seven stage pipeline for instruction execution. The
instruction fetch 1, instruction fetch 2, instruction decode/register file read, execute1, execute2/memory
access1, execute3/memory access2, and register writeback stages operate in an overlapped fashion,
allowing single clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit arithmetic unit (AU), a logic unit (LU), a 32-bit barrel
shifter, a mask-insertion unit (MIU), a condition register manipulation unit (CRU), a count-leading-zeros
unit (CLZ), a 32x32 hardware multiplier array, result feed-forward hardware, and support hardware for
division.
eTPU (continued) Parameter RAM
2.5k
2.5k
2.5k
3k
2.5k
4k
2.5k
Nexus
Class 3
Class 3
Class 3
Class 3
Class 3
Class 3
Class 3
Interrupt Controller
178
channel
210
channel
210
channel
300
channel
231
channel
329
channel
281
channel
Analog to Digital Converter (eQADC)
40
channel
40
channel
40
channel
40
channel
40
channel
40
channel
40
channel
ADC_0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ADC_1
No
Yes
Yes
Yes
Yes
Yes
Yes
Fast Ethernet Controller (FEC)
No
No
Yes
9
No
No
Yes
Yes
10
FlexRay
No
No
No
No
No
No
Yes
FlexRay Nexus
No
No
No
No
No
No
Class 3
Phase Lock Loop (PLL)
FM
FM
FM
FM
FM
FM
FM
Maximum System Frequency
11
80 MHz
80 MHz
132 MHz
132 MHz
132 MHz
132 MHz
132 MHz
Crystal Range
8-20 MHz
8-20 MHz
8-20 MHz
8-20 MHz
8-20 MHz
8-20 MHz
8-20 MHz
40 MHz
Voltage Regulator Controller (VRC)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1
Two-way associative
2
Eight-way associative
3
Four-way associative
4
16-byte flash page size for programming
5
32-byte flash page size for programming
6
May not be externally available in some package configurations
7
Either ADDR[8:31] or ADDR[6:29] can be selected.
8
Updated FlexCAN module with optional individual receive filters
9
The FEC signals are shared with data bus pins DATA[16:31].
10
The FEC signals are shared with the calibration bus.
11
Initial automotive temperature range qualification.
Table 1-1. MPC5500 Family Members (Continued)
MPC5500 Device
MPC5533
MPC5534
MPC5553
MPC5554
MPC5565
MPC5566
MPC5567
Summary of Contents for MPC5553
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