MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
2-22
Freescale Semiconductor
2.2.2
MPC5554 Signals Summary
gives a summary of the MPC5554 external signals and properties.
38
The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. The XTAL pin has no function when bypass mode is
selected and must be grounded.
39
When the FMPLL is configured for external reference mode, the V
DDE5
supply affects the signal levels for the external reference. Refer to
.”
40
The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[0:1] pins. If the EXTCLK function is chosen, the
valid operating voltage for the pin is 1.6–3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V. Refer to
41
V
RC33
is the 3.3 V input for the voltage regulator control.
42
V
RCVSS
is connected internally to V
SSSYN
. V
RCVSS
is not available on the 208 package.
43
Each VDDAn and VSSAn connects to one ADC engine to provide isolation.
44
V
FLASH
is not available on the 208 package; it is connected inside the package to VDD33.
45
V
PP
can be tied to 5.0 V for both the read operation and program/erase operation.
46
Tie the V
STBY
pin to V
SSA0
if the battery-backed internal SRAM is not used.
47
The V
DDEH9
segment can be powered from 3.0–5.0 V for MUX addresses or SSI functions, but must meet the V
DDA1
specifications of 4.5 V to 5.25 V for
analog input function.
48
All pins with pad type pad_fc are driven to the high state if their V
DDE
segment is powered before V
DD33
.
49
The pins are reserved for the clock and inverted clock outputs for the DDR memory interface. In the MPC5553 416-pin package, the two NC pins are isolated
(not shorted together in the package substrate).
Table 2-2. MPC5554 Signal Properties
Signal Names
1
Signal Functions
2
P/
A/
G
I/O
Type
Voltage
3
Pad
Type
4
Status
Pin Labels / Package
During
Reset
5
After
Reset
6
496
7
416
Reset / Configuration Signals
RESET
External Reset Input
P
I
V
DDEH6
SH
RESET /
Up
RESET / Up
AA27
W26
RSTOUT
External Reset Output
P
O
V
DDEH6
SH
RSTOUT /
Low
RSTOUT /
High
W26
V25
PLLCFG[0]_
IRQ[4]_
GPIO[208]
FMPLL Mode Selection
External Interrupt Request
General Purpose I/O
P
A
G
I
I
I/O
V
DDEH6
MH
PLLCFG /
Up
– / Up
AB27
AB25
PLLCFG[1]_
IRQ[5]_
SOUTD_
GPIO[209]
FMPLL Mode Selection
External Interrupt Request
DSPI D Data Out
General Purpose I/O
P
A
A2
G
I
I
O
I/O
V
DDEH6
MH
PLLCFG /
Up
– / Up
AA26
AA24
RSTCFG_
GPIO[210]
Reset Configuration Input
General Purpose I/O
P
A
I
I/O
V
DDEH6
SH
RSTCFG /
Up
– / Up
Y28
V26
BOOTCFG[0:1]_
IRQ[2:3]_
GPIO[211:212]
Boot Configuration Input
External Interrupt Request
General Purpose I/O
P
A
G
I
I
I/O
V
DDEH6
SH
BOOTCFG
/ Down
– / Down
AB26
AA25,
Y24
WKPCFG_
GPIO[213]
Weak Pull Configuration Input
General Purpose I/O
P
G
I
I/O
V
DDEH6
SH
WKPCFG /
Up
– / Up
AB24
Y23
External Bus Interface (EBI)
8
Signals
CS[0:3]_
9
ADDR[8:11]_
GPIO[0:3]
External Chip Selects
External Address Bus
General Purpose I/O
P
A
G
O
I/O
I/O
V
DDE2
F
– / Up
– / Up
10
T7, R5, P5,
R7
P4, P3,
P2, P1
Summary of Contents for MPC5553
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