MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
20-64
Freescale Semiconductor
Depending on the state of the ROOE bit in the DSPI
x
_MCR, the data from the transfer that generated the
overflow is either ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is
shifted in to the shift register. If the ROOE bit is negated, the incoming data is ignored.
20.4.9.7
FIFO Overrun Request (TFUF) or (RFOF)
The FIFO overrun request indicates that at least one of the FIFOs in the DSPI has exceeded its capacity.
The FIFO overrun request is generated by logically OR’ing together the RX FIFO overflow and TX FIFO
underflow signals.
20.4.10 Power Saving Features
The DSPI supports two power-saving strategies:
•
Module disable mode—clock gating of non-memory mapped logic
•
Clock gating of slave interface signals and clock to memory-mapped logic
20.4.10.1 Module Disable Mode
Module disable mode is a module-specific mode that the DSPI can enter to save power. Host software can
initiate the module disable mode by writing a 1 to the MDIS bit in the DSPI
x
_MCR. In module disable
mode, the DSPI is in a dormant state, but the memory mapped registers are still accessible. Certain read
or write operations have a different affect when the DSPI is in the module disable mode. Reading the RX
FIFO pop register will not change the state of the RX FIFO. Likewise, writing to the TX FIFO push register
will not change the state of the TX FIFO. Clearing either of the FIFOs will not have any affect in the
module disable mode. Changes to the DIS_TXF and DIS_RXF fields of the DSPI
x
_MCR will not have
any affect in the module disable mode. In the module disable mode, all status bits and register flags in the
DSPI will return the correct values when read, but writing to them will have no affect. Writing to the
DSPI
x
_TCR during module disable mode will not have any affect. Interrupt and DMA request signals
cannot be cleared while in the module disable mode.
20.4.10.2 Slave Interface Signal Gating
The DSPI’s module enable signal is used to gate slave interface signals such as address, byte enable,
read/write and data. This prevents toggling slave interface signals from consuming power unless the DSPI
is accessed.
20.5
Initialization/Application Information
20.5.1
How to Change Queues
DSPI queues are not part of the DSPI module, but the DSPI includes features in support of queue
management. Queues are primarily supported in SPI configuration. This section presents an example of
how to change queues for the DSPI.
1. The last command word from a queue is executed. The EOQ bit in the command word is set to
indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is sampled, the EOQ
flag (EOQF) in the DSPI
x
_SR is set.
Summary of Contents for MPC5553
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