MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
21-23
Toggling the TE bit from 0 to 1 automatically loads the transmit shift register with a preamble of 10 logic
1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from
the eSCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit
position.
The eSCI hardware supports odd or even parity. When parity is enabled, the most significant bit (Msb) of
the data character is the parity bit.
The transmit data register empty flag, TDRE, in the eSCI status register (ESCI
x
_SR) becomes set when
the eSCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the eSCI
data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in
eSCI control register 1 (ESCI
x
_CR1) is also set, the TDRE flag generates a transmitter interrupt request.
When the transmit shift register is not transmitting a frame, the TXD output goes to the idle condition,
logic 1. If at any time software clears the TE bit in eSCI control register 1 (ESCI
x
_CR1), the transmitter
enable signal goes low and the TXD output goes idle.
If software clears TE while a transmission is in progress (ESCI
x
_CR1[TC] = 0), the frame in the transmit
shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always
wait for TDRE to go high after the last frame before clearing TE.
To separate messages with preambles with minimum idle line time, use the following sequence between
messages:
1. Write the last byte of the first message to ESCI
x
_DR.
2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift
register.
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the first byte of the second message to ESCI
x
_DR.
21.4.4.3
Break Characters
Setting the break bit, SBK, in eSCI control register 1 (ESCI
x
_CR1) loads the transmit shift register with a
break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character
length depends on the M bit in the eSCI control register 1 (ESCI
x
_CR1) and on the BRK13 bit in the eSCI
control register 2 (ESCI
x
_CR2). As long as SBK is set, the transmitter logic continuously loads break
characters into the transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the
end of a break character guarantees the recognition of the start bit of the next frame.
NOTE
LIN 2.0 now requires that a break character is always 13 bits long, so the
BRK13 bit should always be set to 1. The eSCI will work with BRK13=0,
but it will violate LIN 2.0.
The eSCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be. Receiving a break character has the following effects on eSCI
registers:
•
Sets the framing error flag, FE.
•
Sets the receive data register full flag, RDRF.
•
Clears the eSCI data register (ESCI
x
_DR).
Summary of Contents for MPC5553
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