MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
24-11
24.4.4.7
SAMPLE Instruction
The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input
pins and just before the boundary scan register cells at the output pins. This sampling occurs on the rising
edge of TCK in the capture-DR state when the SAMPLE instruction is active. The sampled data is viewed
by shifting it through the boundary scan register to the TDO output during the Shift-DR state. There is no
defined action in the update-DR state. Both the data capture and the shift operation are transparent to
system operation.
24.4.4.8
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction has two functions:
•
First, the SAMPLE portion of the instruction obtains a sample of the system data and control
signals present at the MCU input pins and just before the boundary scan register cells at the output
pins. This sampling occurs on the rising edge of TCK in the capture-DR state when the
SAMPLE/PRELOAD instruction is active. The sampled data is viewed by shifting it through the
boundary scan register to the TDO output during the shift-DR state. Both the data capture and the
shift operation are transparent to system operation.
•
Secondly, the PRELOAD portion of the instruction initializes the boundary scan register cells
before selecting the EXTEST or CLAMP instructions to perform boundary scan tests. This is
achieved by shifting in initialization data to the boundary scan register during the shift-DR state.
The initialization data is transferred to the parallel outputs of the boundary scan register cells on
the falling edge of TCK in the update-DR state. The data is applied to the external output pins by
the EXTEST or CLAMP instruction. System operation is not affected.
24.4.5
Boundary Scan
The boundary scan technique allows signals at component boundaries to be controlled and observed
through the shift-register stage associated with each pad. Each stage is part of a larger boundary scan
register cell, and cells for each pad are interconnected serially to form a shift-register chain around the
border of the design. The boundary scan register consists of this shift-register chain, and is connected
between TDI and TDO when the EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded.
The shift-register chain contains a serial input and serial output, as well as clock and control signals.
24.5
Initialization/Application Information
The test logic is a static logic design, and TCK can be stopped in either a high or low state without loss of
data. However, the system clock is not synchronized to TCK internally. Any mixed operation using both
the test logic and the system functional logic requires external synchronization.
To initialize the JTAGC module and enable access to registers, the following sequence is required:
1. Set the JCOMP signal to logic 1, thereby enabling the JTAGC TAP controller.
2. Load the appropriate instruction for the test or action to be performed.
Summary of Contents for MPC5553
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