MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
B-4
Freescale Semiconductor
B.3
Device Specific Information
The various address bus, data bus and bus control signals are sourced from different device signals
depending on the MPC5500 family being used as detailed in the following sections.
CAL_CS[1]
Chip Select
No Connect
CS[1]_
ADDR[9]_
GPIO[1]
CAL_CS[2]
Chip Select
BR
CAL_ADDR[10]_
FEC_MDC_
CAL_CS[2]_
GPIO[72]
CS[2]_
ADDR[10]_
GPIO[2]
CAL_CS[3]
Chip Selects
BG
CAL_ADDR[11]_
FEC_MDIO_
CAL_CS[3]_
GPIO[73]
CS[3]_
ADDR[11]_
GPIO[3]
CAL_DATA[0:15]
Data Bus
DATA[16:31]_
FEC_(signals)
2
_
CAL_DATA[0:15]_
GPIO[44:59]
DATA[0:15]_
GPIO[28:43]
CAL_OE
Output Enable
OE_
GPIO[68]
OE_
GPIO[68]
CAL_RD_WR
Read/Write
RD_WR_
GPIO[62]
RD_WR_
GPIO[62]
CAL_TS
Transfer Start
TS_
GPIO[69]
TS_
GPIO[69]
CAL_TA
Transfer Acknowledge
TA_
GPIO[70]
TA_
GPIO[70]
CAL_WE/BE[0:1]
Write/Byte Enable
WE[/BE[2:3]
3
_
CAL_WE/BE[0:1]_
GPIO[66:67]
WE/BE[0:1]_
GPIO[64:65]
Clock Synthesizer (1)
CLKOUT
System Clock Output
CLKOUT
CLKOUT
1
The BR and BG functions are not implemented on the MPC5553 and are replaced by FEC and calibration functions. The
pin name on the ball map, however, does remain BR and BG. The primary functions for these pins are CAL_ADDR[10]
and CAL_ADDR[11], respectively.
2
Refer to the Signals chapter for a complete list of FEC signals.
3
The function for the WE/BE[2:3]_CAL_WE/BE[0:1]_GPIO[66:67] pins is specified in the SIU. When configured for EBI,
the write enable or byte enable operation is specified in the EBI_BR0 through EBI_BR3 registers. When configured for
the Calibration bus, the write enable or byte enable operation is specified in the EBI_CAL_BR0 through EBI_CAL_BR3
registers for each chip select region.
Table B-1. Calibration Bus Signals (Continued)
VertiCal Signal Name
Function
Device Implementation Signal Name
MPC5553
MPC5554
Summary of Contents for MPC5553
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