System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual,
Rev. 5
Freescale Semiconductor
6-19
6.3.1.12
Pad Configuration Registers (SIU_PCR)
The following subsections define the pad configuration registers (PCR) in the SIU_PCR segment. These
registers define the pad configuration for all configurable device pins that specify that active function,
direction, and static electrical attributes for the pin. The information presented pertains to which bits and
fields are active for a given pin or group of pins, and the reset state of the register.
The reset state of the SIU_PCRs presented in this section is the value before the BAM program executes.
The BAM program can change some pad configuration registers based on the reset configuration. Refer
to
Chapter 16, “Boot Assist Module (BAM)
,” for more detailed information.
The SIU_PCRs are 16-bit registers that are read or written as 16-bit values aligned on 16-bit boundaries,
or as 32-bit values aligned on 32-bit address boundaries.
NOTE
The fields available in a given SIU_PCR depend on the type of pad it
controls. Refer to the specific SIU_PCR definition.
All MPC5553/MPC5554 pin names begin with the primary function, followed by the alternate function,
and then GPIO. In some cases the third function may not be GPIO. Those exceptions are noted in the
Address: Base + 0x0030
Access: Read / Write[28:31]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address: Base + 0x0030
Access: Read / Write[28:31]
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
0
0
DFL
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-13. External IRQ Digital Filter Register (SIU_IDFR)
Table 6-15. SIU_IDFR Field Descriptions
Register Bit Range
Field Name
Function
0–27
Reserved.
28–31
DFL
Digital filter length. Defines the digital filter period on the IRQ[n] inputs according to the following
equation:
For a 100 MHz system clock, this gives a range of 20 ns to 328 µs. The minimum time of three
clocks accounts for synchronization of the IRQ input pins with the system clock.
Filter Period
SystemClockPeriod
2
DFL
1 S
ystemClockPeriod
+
=
Summary of Contents for MPC5553
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