System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual,
Rev. 5
6-42
Freescale Semiconductor
6.3.1.12.22
MPC5554: Pad Configuration Registers 60–61 (SIU_PCR60–SIU_PCR61)
NOTE
The MPC5553 does not implement PCRs 60–61; therefore, these registers
are reserved on the MPC5553.
The SIU_PCR60–SIU_PCR61 registers control the pin function, direction, and static electrical attributes
of the TSIZ[0:1]_GPIO[60:61] pins.
Figure 6-35. MPC5554: TSIZ[0:1]_GPIO[60:61] Pad Configuration Registers (SIU_PCR60–SIU_PCR61)
Refer to
for bit field definitions.
6.3.1.12.23
Pad Configuration Register 62 (SIU_PCR62)
The SIU_PCR62 register controls the pin function, direction, and static electrical attributes of the
RD_WR_GPIO[62] pin. Because the MPC5553 calibration bus interface (CBI) and external bus interface
(EBI) share the same physical bus, the MPC5553 uses the RD_WR signal for the CBI as well as the EBI.
Figure 6-36. RD_WR_GPIO[62] Pad Configuration Register (SIU_PCR62)
Address: Base + 0x00B8 and Base + 0x00BA
Access: Read / write[5:11, 14:15]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
PA
OBE
1
1
When configured as TSIZ[0:1], the OBE bit has no effect. When configured as GPO, set the OBE bit to 1.
IBE
2
2
When configured as TSIZ[0:1] or GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. Clear the
IBE to 0 to reduce power consumption. When configured as GPI, set the IBE bit to 1.
DSC
ODE
3
3
When configured as TSIZ[0:1], clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0
0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as TSIZ[0:1].
WPS
W
RESET:
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
Address: Base + 0x00BC
Access: Read / write[5:11, 14:15]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
PA
OBE
1
1
When configured as RD_WR, the OBE bit has no effect. When configured as GPO, set the OBE bit to 1.
IBE
2
2
When configured as RD_WR, GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. Clearing the
IBE bit to 0 reduces power consumption. When configured as GPI, set the IBE bit to 1.
DSC
ODE
3
3
When configured as RD_WR, clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0
0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as RD_WR.
WPS
W
RESET:
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
Summary of Contents for MPC5553
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