System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual,
Rev. 5
6-50
Freescale Semiconductor
6.3.1.12.34
MPC5554: Pad Configuration Register 72 (SIU_PCR72)
The SIU_PCR72 register controls the pin function, direction, and static electrical attributes of the
BR_GPIO[72] pin.
Figure 6-46. MPC5554: BR_GPIO[72] Pad Configuration Register (SIU_PCR72)
Refer to
for bit field definitions.
6.3.1.12.35
MPC5553: Pad Configuration Register 73 (SIU_PCR73)
The SIU_PCR73 register controls the pin function, direction, and static electrical attributes of the
BG(CAL_ADDR[11])_FEC_MDIO_CAL_CS[3]_GPIO[73] pin. The BG function is not available on the
MPC5553. Therefore, the CAL_ADDR[11] signal serves as the primary signal function with a PA setting
of 0b001. This register allows selection of the CAL_ADDR[11], FEC_MDIO, CAL_CS[3], and GPIO
functions.
Figure 6-47. MPC5553: BG(CAL_ADDR[11])_FEC_MDIO_CAL_CS[3]_GPIO[73]
Pad Configuration Register (SIU_PCR73)
Address: Base + 0x00D0
Access: Read / write[5:11, 14:15]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
PA
OBE
1
1
When configured as BR, the OBE bit has no effect. When configured as GPO, set the OBE bit to 1.
IBE
2
2
When configured as BR or GPO, set the IBE bit to 1 to reflect the pin state in the corresponding GPDI register. Clearing the IBE
bit to 0 reduces power consumption. When configured as GPI, set the IBE bit to 1.
DSC
ODE
3
3
When configured as BR, and external master operation is enabled with external arbitration, clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0
0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as BR.
WPS
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Address: Base + 0x00D2
Access: Read / write[3:11, 14:15]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
PA
1
1
The BG function is not available on the MPC5553. Set the PA field to 0b001 or 0b011 to select CAL_ADDR[11] to use the
calibration bus.
OBE
2
2
When configured as CAL_ADDR[11], FEC_MDIO, or CAL_CS[3], the OBE bit has no effect. When configured as GPO, set the
OBE bit to 1.
IBE
3
3
When configured as CAL_ADDR[11], FEC_MDIO, CAL_CS[3], or GPO, set the IBE bit to 1 to reflect the pin state in the
corresponding GPDI register. Clearing the IBE bit to 0 reduces power consumption. When configured as GPI, set the IBE bit to 1.
DSC
ODE
4
4
When configured as CAL_ADDR[11] or CAL_CS[3], clear the ODE bit to 0.
HYS
5
5
If the external master operation is enabled, clear the HYS bit to 0.
0
0
WPE
6
6
Refer to the EBI section for weak pullup settings when configured as CAL_ADDR[11] or CAL_CS[3].
WPS
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Summary of Contents for MPC5553
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