MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
9-30
Freescale Semiconductor
9.4
Functional Description
This section provides an overview of the microarchitecture and functional operation of the eDMA module.
9.4.1
eDMA Microarchitecture
The eDMA module is partitioned into two major modules: the eDMA engine and the transfer control
descriptor local memory. Additionally, the eDMA engine is further partitioned into four submodules,
which are detailed below.
•
eDMA engine
— Address path: This module implements registered versions of two channel transfer control
descriptors: channel ‘x’ and channel ‘y,’ and is responsible for all the master bus address
calculations. All the implemented channels provide the exact same functionality. This
hardware structure allows the data transfers associated with one channel to be preempted after
the completion of a read/write sequence if a higher priority channel service request is asserted
while the first channel is active. After a channel is activated, it runs until the minor loop is
completed unless preempted by a higher priority channel. This capability provides a
mechanism (optionally enabled by EDMA_CPR
n
[ECP]) where a large data move operation
can be preempted to minimize the time another channel is blocked from execution.
When any other channel is activated, the contents of its transfer control descriptor is read from
the local memory and loaded into the registers of the other address path channel{x,y}. After
the inner minor loop completes execution, the address path hardware writes the new values for
the TCD
n
.{SADDR, DADDR, CITER} back into the local memory. If the major iteration
count is exhausted, additional processing is performed, including the final address pointer
updates, reloading the TCDn.CITER field, and a possible fetch of the next TCDn from memory
as part of a scatter/gather operation.
— Data path: This module implements the actual bus master read/write datapath. It includes 32
bytes of register storage (matching the maximum transfer size) and the necessary mux logic to
support any required data alignment. The system read data bus is the primary input, and the
system write data bus is the primary output.
The address and data path modules directly support the 2-stage pipelined system bus. The
address path module represents the 1st stage of the bus pipeline (the address phase), while the
data path module implements the 2nd stage of the pipeline (the data phase).
— Program model/channel arbitration: This module implements the first section of eDMA’s
programming model as well as the channel arbitration logic. The programming model registers
are connected to the slave bus (not shown). The eDMA peripheral request inputs and eDMA
interrupt request outputs are also connected to this module (via the Control logic).
— Control: This module provides all the control functions for the eDMA engine. For data
transfers where the source and destination sizes are equal, the eDMA engine performs a series
of source read, destination write operations until the number of bytes specified in the inner
‘minor loop’ byte count has been moved.
A minor loop interation is defined as the number of bytes to transfer (
n
bytes) divided by the
transfer size. Transfer size is defined as the following”
if (ssize < dsize)
transfer size = destination transfer size (# of bytes)
else
transfer size = source transfer size (# of bytes)
Summary of Contents for MPC5553
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