MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
12-23
12.4.1.7
Bus Monitor
When enabled (via the BME bit in the EBI_BMCR), the bus monitor detects when no TA assertion is
received within a maximum timeout period for non-chip select accesses (that is, accesses that use external
TA). The timeout for the bus monitor is specified by the BMT field in the EBI_BMCR. Each time a timeout
error occurs, the BMTF bit is set in the EBI_TESR. The timeout period is measured in external bus
(CLKOUT) cycles. Thus the effective real-time period is multiplied (by 2 or 4) when a configurable bus
speed mode is used, even though the BMT field itself is unchanged.
12.4.1.8
Port Size Configuration per Chip Select (16 or 32 Bits)
The EBI supports memories with data widths of 16 or 32 bits. The port size for a particular chip select is
configured by writing the PS bit in the corresponding base register.
12.4.1.9
Port Size Configuration per Calibration Chip Select (16 Bits)
The port size for calibration must be 16 bits wide.
12.4.1.10 Configurable Wait States
From 0 to 15 wait states can be programmed for any cycle that the memory controller generates, via the
SCY bits in the appropriate option register. From zero to three wait states between burst beats can be
programmed using the BSCY bits in the appropriate option register.
12.4.1.11 Four Chip Select (CS[0:3]) Signals
The EBI contains four chip select signals, controlling four independent memory banks. See
Section 12.4.1.5, “Memory Controller with Support for Various Memory Types
select bank configuration.
12.4.1.12 Support for Dynamic Calibration with Up to 4 Chip Selects
The EBI contains four calibration chip select signals, controlling four independent memory banks on an
optional second external bus for calibration. See
Section 12.4.2.12, “Calibration Bus Operation —
” for more details on using the calibration bus.
12.4.1.13 Four Write/Byte Enable (WE/BE) Signals — Only MPC5554 and 416 BGA
of MPC5553
In the MPC5554 and in the 416 BGA of the MPC5553, the functionality of the WE[0:3]/BE[0:3] signals
depends on the value of the WEBS bit in the corresponding base register. Setting WEBS to 1 configures
these pins as BE[0:3], while resetting it to 0 configures them as WE[0:3]. WE[0:3] are asserted only during
write accesses, while BE[0:3] is asserted for both read and write accesses. The timing of the
WE[0:3]/BE[0:3] signals remains the same in either case.
The upper write/byte enable (WE0/BE0) indicates that the upper eight bits of the data bus (DATA[0:7])
contain valid data during a write/read cycle. The upper middle write/byte enable (WE1/BE1) indicates that
the upper middle eight bits of the data bus (DATA[8:15]) contain valid data during a write/read cycle. The
lower middle write/byte enable (WE2/BE2) indicates that the lower middle eight bits of the data bus
(DATA[16:23]) contain valid data during a write/read cycle. The lower write/byte enable (WE3/BE3)
indicates that the lower eight bits of the data bus (DATA[24:31]) contain valid data during a write/read
cycle.
Summary of Contents for MPC5553
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