MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
12-72
Freescale Semiconductor
12.5.5.2
Arbitration with No Arb Pins (Master/Slave only)
Without arbitration pins, a dual-master system is impossible, because these is no way for the two masters
to take turns driving the external bus without conflicts. However, a master/slave system is possible, as
described below.
To implement a master/slave system with an MCU that has no arbitration pins (BB, BG, BR), the user must
configure the master MCU for internal arbitration (EARB=0 in EBI_MCR) and the slave MCU for
external arbitration (EARB=1). Internally on an MCU with no arbitration pins, the BR, BG, and BB signals
to the EBI will be tied negated. This means that the slave MCU will never receive bus grant asserted, so it
will never attempt to start an access on the external bus. The master MCU will never receive bus request
or bus busy asserted, so it will maintain ownership of the bus without any arbitration delays. In the
erroneous case that the slave MCU executes internal code that attempts to access external address space,
that access will never get external and will eventually time-out in the slave MCU.
12.5.5.3
Transfer Size with No TSIZ Pins (Master/Master or Master/Slave)
Because there are no TSIZ pins to communicate transfer size from master MCU to slave MCU, the internal
SIZE field of the EBI_MCR must be used on the slave MCU (by setting SIZEN=1 in slave’s EBI_MCR).
Anytime the master MCU needs to read or write the slave MCU with a different transfer size than the
current value of the slave’s SIZE field, the master MCU must first write the slave’s SIZE field with the
correct size for the subsequent transaction.
12.5.5.4
No Transfer Acknowledge (TA) Pin
If an MCU has no TA pin available, this restricts the MCU to chip select accesses only. Non-chip select
accesses have no way for the EBI to know which cycle to latch the data. The EBI has no built-in protection
to prevent non-chip select accesses in this scenario; it is up to the user to make certain they set up chip
selects and external memories correctly to ensure all external accesses fall in a valid chip select region.
12.5.5.5
No Transfer Error (TEA) Pin
If an MCU has no TEA pin available, this eliminates the feature of terminating an access with TEA. This
means if an access times out in the EBI bus monitor, the EBI (master) will still terminate the access early,
but there will be no external visibility of this termination, so the slave device might end up driving data
much later, when a subsequent access is already underway. Therefore, the EBI bus monitor should be
disabled when no TEA pin exists.
12.5.5.6
No Burst Data in Progress (BDIP) Pin
If an MCU has no BDIP pin available, this eliminates burst support only if the burstable memory being
used requires BDIP to burst. Many external memories use a self-timed configurable burst mechanism that
does not require a dynamic burst indicator. Check the applicable external memory specification to see if
BDIP is required in your system.
12.5.6
Summary of Differences from MPC5xx
Below is a summary list of the significant differences between this EBI used in the MPC5553/MPC5554
and that of the MPC5xx parts:
•
SETA feature is no longer available
— Chip select devices cannot use external TA, instead must use wait state configuration.
Summary of Contents for MPC5553
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