MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
13-23
13.4
Functional Description
13.4.1
Flash Bus Interface Unit (FBIU)
The FBIU interfaces between the system bus and the flash memory interface unit and generates read and
write enables, the flash array address, write size, and write data as inputs to the flash memory interface unit
(MI). The FBIU captures read data from the MI and drives it on the system bus. Up to two lines (one line
is a 256-bit width) of data or instructions are buffered by the FBIU. Lines can be prefetched in advance of
being requested by the system bus interface, allowing single-cycle read data responses on buffer hits.
Several prefetch control algorithms are available for controlling line read buffer fills. Prefetch triggering
can be restricted to instruction accesses only, data accesses only, or can be unrestricted. Prefetch triggering
can also be controlled on a per-master basis.
Access protections can be applied on a per-master basis for both reads and writes to support security and
privilege mechanisms.
13.4.1.1
FBIU Basic Interface Protocol
The FBIU interfaces to the flash array by driving addresses and read or write enable signals to the flash
memory interface unit. The access time of the flash is determined by the settings of the wait-state control
bits in the FLASH_BIUCR, as well as the pipelining of addresses.
The FBIU also has the capability of extending the normal system bus access timing by inserting additional
primary (initial access) wait states for reads and burst reads. This capability is provided to allow emulation
of other memories which have different access time characteristics.
13.4.1.2
FBIU Access Protections
The FBIU provides hardware configurable access protections for both read and write cycles from masters.
It allows restriction of read and write requests on a per-master basis. The FBIU also supports software
configurable access protections. Detection of a protection violation results in an error response from the
FBIU to the system bus.
13.4.1.3
Flash Read Cycles—Buffer Miss
Read data is normally stored in the least-recently updated line read buffer in parallel with the requested
data being forwarded to the system bus.
13.4.1.4
Flash Read Cycles—Buffer Hit
Single clock read responses to the system bus are possible with the FBIU when the requested read access
is buffered.
13.4.1.5
Flash Access Pipelining
Accesses to the flash array can be pipelined by driving a subsequent access address and control signals
while waiting for the current access to complete. Pipelined access requests are always run to completion
and are not aborted by the FBIU. Request pipelining allows for improved performance by reducing the
access latency seen by the system bus master. Access pipelining can be applied to both read and write
cycles by the flash array.
Summary of Contents for MPC5553
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