MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
14-38
Freescale Semiconductor
Both buffer (TXB) and frame (TFINT) interrupts may be generated as determined by the settings in the
EIMR.
The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If
the transmit frame length exceeds MAX_FL bytes, the BABT interrupt will be asserted but the entire frame
will be transmitted (no truncation).
To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When the TCR[GTS]
is set, the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues
transmission until the current frame either finishes or terminates with a collision. After the transmitter has
stopped, the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes
transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
14.4.7
FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can perform address
recognition, CRC checking, short frame checking, and maximum frame length checking.
When the driver enables the FEC receiver by asserting ECR[ETHER_EN], it will immediately start
processing receive frames. When FEC_RX_DV asserts, the receiver will first check for a valid PA/SFD
header. If the PA/SFD is valid, it will be stripped and the frame will be processed by the receiver. If a valid
PA/SFD is not found, the frame will be ignored.
In serial mode, the first 16 bit times of FEC_RX_D0 following assertion of FEC_RX_DV are ignored.
Following the first 16 bit times the data sequence is checked for alternating 1/0s. If a 11 or 00 data sequence
is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the data
sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is detected,
the PA/SFD sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur,
but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.
After a collision window (64 bytes) of data has been received and if address recognition has not rejected
the frame, the receive FIFO is signalled that the frame is “accepted” and may be passed on to the DMA.
If the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified
to “reject” the frame. Thus, no collision fragments are presented to the user except late collisions, which
indicate serious LAN problems.
During reception, the Ethernet controller checks for various error conditions and after the entire frame is
written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the
M, BC, MC, LG, NO, CR, OV and TR status bits, and the frame length. See
” for more details.
Receive buffer (RXB) and frame interrupts (RFINT) may be generated if enabled by the EIMR register. A
receive error interrupt is babbling receiver error (BABR). Receive frames are not truncated if they exceed
the max frame length (MAX_FL); however, the BABR interrupt will occur and the LG bit in the receive
buffer descriptor (RxBD) will be set. See
Section 14.5.2, “Ethernet Receive Buffer Descriptor (RxBD)
for more details.
When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits
into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT
bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory.
The Ethernet controller then waits for a new frame.
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