MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
19-82
Freescale Semiconductor
RFIFO. Using POPNXTPTR and RFCTR, the absolute addresses for pop next data pointer and receive
next data pointer can be calculated using the following formulas:
Pop Next Data Pointer Address= RFIFO
n
_BASE_A POPNXTPTR
n
*4
Receive Next Data Pointer Address = RFIFO
n
_BASE_A
[(POPNXTPTR
n
+ RFCTR
n
) mod RFIFO_DEPTH] * 4
where
•
a
mod b
returns the remainder of the division of
a
by
b
.
•
RFIFO
n
_BASE_ADDRESS is the smallest memory mapped address allocated to an RFIFO
n
entry.
•
RFIFO_DEPTH is the number of entries contained in a RFIFO - four in this implementation.
When a new message arrives and RFIFO
n
is not full, the eQADC copies its contents into the entry pointed
by receive next data pointer. The RFIFO counter EQADC_FISR
n
[RFCTR
n
incremented by 1, and the receive next data pointer
n
is also incremented by 1 (or wrapped around) to point
to the next empty entry in RFIFO
n
. However, if the RFIFO
n
is full, the eQADC sets the
EQADC_FISR
n
[RFOF] (see Section 19.3.2.8). The RFIFO
n
will not overwrite the older data in the
RFIFO, the new data will be ignored, and the receive next data pointer
n
is not incremented or wrapped
around. RFIFO
n
is full when the receive next data pointer
n
equals the pop next data pointer
n
and
RFCTR
n
is not 0. RFIFO
n
is empty when the receive next data pointer
n
equals the pop next data pointer
n
and RFCTR
n
is 0.
When the eQADC RFIFO pop register
n
is read and the RFIFO
n
is not empty, the RFIFO counter RFCTR
n
is decremented by 1, and the pop next data pointer is incremented by 1 (or wrapped around) to point to the
next RFIFO entry.
When the eQADC RFIFO pop register
n
is read and RFIFO
n
is empty, eQADC will not decrement the
counter value and the pop next data pointer
n
will not be updated. The read value will be undefined.
Figure 19-46. RFIFO Diagram
The detailed behavior of the pop next data pointer and receive next data pointer is described in the example
shown in
where an RFIFO with 16 entries is shown for clarity of explanation, the actual
Pop Next
Data Entry 1
Data Entry 2
Control Signals
RFIFO
Counter Control
Logic
Data Pointer *
Receive Next
Data Pointer *
Data from
External
Device or
from
On-Chip
Read
from Bus
Interface
by CPU
or DMA
DMA Done
Interrupt/DMA Request
All RFIFO entries are memory mapped and the entries addressed by these pointers
can have their absolute addresses calculated using POPNXTPTR and RFCTR.
*
RFIFO
Pop Register
ADCs
Summary of Contents for MPC5553
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