MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
19-101
NOTE
On the master, the FCK is not used as a clock. Although, the eQADC SSI
behavior is described in terms of the FCK positive and negative edges, all
eQADC SSI related signals (SDI, SDS, SDO, and FCK) are synchronized
by the system clock on the master side. There are no restrictions regarding
the use of the FCK as a clock on the slave device.
19.4.8.1.1
Abort Feature
The master indicates it is aborting the current transfer by negating SDS before the whole data frame has
being shifted out, that is the 26th bit of data being transferred has not being shifted out. The eQADC
ignores the incompletely received message. The eQADC re-sends the aborted message whenever the
corresponding CFIFO becomes again the highest priority CFIFO with commands bound for an external
command buffer that is not full. Refer to
Section 19.4.3.2, “CFIFO Prioritization and Command Transfer
,”
for more information on aborts and CFIFO priority.
19.4.8.2
Baud Clock Generation
As shown in
, the baud clock generator divides the system clock to produce the baud clock.
The EQADC_SSICR[BR] field (see Section 19.3.2.12) selects the system clock divide factor as in
.
1
Figure 19-57. Synchronous Serial Interface Protocol Timing
1.Maximum FCK frequency is highly dependable on track delays, master pad delays, and slave pad delays.
BaudClockFrequency
SystemClockFrequency MHz
SystemClockDivideFactor
----------------------------------------------------------------------------------------
=
NOTE:
t
MDT
= Minimum t
DT
is programmable and defined in
Section 18.3.2.12, ‘eQADC SSI Control Register (EQADC_SSICR).’
FCK
SDS
Master Sample
Input
SDO
1
End
Transmission
t
DT
Slave Sample
Input
2
3
...
23
24
25
26
1
2
3
...
23
24
25
msb
msb
26
1
2
3
...
23
24
25
26
1
2
3
...
23
24
25
msb
msb
26
1
msb
Begin
Transmission
End
Transmission
Begin
Transmission
SDI
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