MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
20-36
Freescale Semiconductor
20.4.3.1
SPI Master Mode
In SPI master mode the DSPI initiates the serial transfers by controlling the serial communications clock
(SCK) and the peripheral chip select (PCS) signals. The SPI command field in the executing TX FIFO
entry determines which CTARs will be used to set the transfer attributes and which PCS signal to assert.
The command field also contains various bits that help with queue management and transfer protocol. See
Section 20.3.2.6, “DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
,” for details on the SPI command
fields. The data field in the executing TX FIFO entry is loaded into the shift register and shifted out on the
serial out (SOUT) pin. In SPI master mode, each SPI frame to be transmitted has a command associated
with it allowing for transfer attribute control on a frame by frame basis.
20.4.3.2
SPI Slave Mode
In SPI slave mode the DSPI responds to transfers initiated by an SPI bus master. The DSPI does not initiate
transfers. Certain transfer attributes such as clock polarity, clock phase and frame size must be set for
successful communication with an SPI master. The SPI slave mode transfer attributes are set in the
DSPI
x
_CTAR0.
20.4.3.3
FIFO Disable Operation
The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX FIFO. The DSPI
operates as a double-buffered simplified SPI when the FIFOs are disabled. The TX and RX FIFOs are
disabled separately. The TX FIFO is disabled by writing a 1 to the DIS_TXF bit in the DSPI
x
_MCR. The
RX FIFO is disabled by writing a 1 to the DIS_RXF bit in the DSPI
x
_MCR.
The FIFO disable mechanisms are transparent to the user and to host software; transmit data and
commands are written to the DSPI
x
_PUSHR and received data is read from the DSPI
x
_POPR. When the
TX FIFO is disabled, the TFFF, TFUF, and TXCTR fields in DSPI
x
_SR behave as if there is a one-entry
FIFO but the contents of the DSPI
x
_TXFRs and TXNXTPTR are undefined. When the RX FIFO is
disabled, the RFDF, RFOF, and RXCTR fields in the DSPI
x
_SR behave as if there is a one-entry FIFO but
the contents of the DSPI
x
_RXFRs and POPNXTPTR are undefined.
The TX and RX FIFOs should be disabled only if the application's operating mode requires the FIFO to
be disabled. A FIFO must be disabled before it is accessed. Failure to disable a FIFO prior to a first FIFO
access is not supported, and may result in incorrect results.
20.4.3.4
Transmit First In First Out (TX FIFO) Buffering Mechanism
The TX FIFO functions as a buffer of SPI data and SPI commands for transmission. The TX FIFO holds
four entries, each consisting of a command field and a data field. SPI commands and data are added to the
TX FIFO by writing to the DSPI push TX FIFO register (DSPI
x
_PUSHR). For more information on
DSPI
x
_PUSHR, refer to
Section 20.3.2.6, “DSPI PUSH TX FIFO Register (DSPIx_PUSHR)
.” TX FIFO
entries can only be removed from the TX FIFO by being shifted out or by flushing the TX FIFO.
The TX FIFO counter field (TXCTR) in the DSPI status register (DSPI
x
_SR) indicates the number of valid
entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data is
transferred into the shift register from the TX FIFO. For more information on DSPI
x
_SR, refer to
Section 20.3.2.4, “DSPI Status Register (DSPIx_SR)
The TXNXTPTR field indicates which TX FIFO entry will be transmitted during the next transfer. The
TXNXTPTR contains the positive offset from DSPI
x
_TXFR0 in number of 32-bit registers. For example,
TXNXTPTR equal to two means that the DSPI
x
_TXFR2 contains the SPI data and command for the next
Summary of Contents for MPC5553
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