MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor
20-63
Each condition has a flag bit and a request enable bit. The flag bits are described in the
“DSPI Status Register (DSPIx_SR)
” and the request enable bits are described in the
“DSPI DMA/Interrupt Request Select and Enable Register (DSPIx_RSER)
.” The TX FIFO fill flag
(TFFF) and RX FIFO drain flag (RFDF) generate interrupt requests or DMA requests depending on the
TFFF_DIRS and RFDF_DIRS bits in the DSPI
x
_RSER.
20.4.9.1
End of Queue Interrupt Request (EOQF)
The end of queue request indicates that the end of a transmit queue is reached. The end of queue request
is generated when the EOQ bit in the executing SPI command is asserted and the EOQF_RE bit in the
DSPI
x
_RSER is asserted. See the EOQ bit description in
Section 20.3.2.4, “DSPI Status Register
that illustrate when EOQF is set.
20.4.9.2
Transmit FIFO Fill Interrupt or DMA Request (TFFF)
The transmit FIFO fill request indicates that the TX FIFO is not full. The transmit FIFO fill request is
generated when the number of entries in the TX FIFO is less than the maximum number of possible entries,
and the TFFF_RE bit in the DSPI
x
_RSER is asserted. The TFFF_DIRS bit in the DSPI
x
_RSER selects
whether a DMA request or an interrupt request is generated.
20.4.9.3
Transfer Complete Interrupt Request (TCF)
The transfer complete request indicates the end of the transfer of a serial frame. The transfer complete
request is generated at the end of each frame transfer when the TCF_RE bit is set in the DSPI
x
_RSER. See
Section 20.3.2.4, “DSPI Status Register (DSPIx_SR)
and
that illustrate when TCF is set.
20.4.9.4
Transmit FIFO Underflow Interrupt Request (TFUF)
The transmit FIFO underflow request indicates that an underflow condition in the TX FIFO has occurred.
The transmit underflow condition is detected only for DSPI modules operating in slave mode and SPI
configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in slave mode and SPI
configuration is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while
the TFUF_RE bit in the DSPI
x
_RSER is asserted, an interrupt request is generated.
20.4.9.5
Receive FIFO Drain Interrupt or DMA Request (RFDF)
The receive FIFO drain request indicates that the RX FIFO is not empty. The receive FIFO drain request
is generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in the
DSPI
x
_RSER is asserted. The RFDF_DIRS bit in the DSPI
x
_RSER selects whether a DMA request or an
interrupt request is generated.
20.4.9.6
Receive FIFO Overflow Interrupt Request (RFOF)
The receive FIFO overflow request indicates that an overflow condition in the RX FIFO has occurred. A
receive FIFO overflow request is generated when RX FIFO and shift register are full and a transfer is
initiated. The RFOF_RE bit in the DSPI
x
_RSER must be set for the interrupt request to be generated.
1
The FIFO Overrun condition is created by OR-ing the TFUF and RFOF flags together.
Summary of Contents for MPC5553
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