MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
21-40
Freescale Semiconductor
21.4.10.5 LIN Setup
Because the eSCI is for general-purpose use, some of the settings are not applicable for LIN operation. The
following setup applies for most applications, regardless of which kind of LIN slave is addressed:
a) The module is enabled by writing the ESCI
x
_CR2[MDIS] bit to 0.
b) Both transmitter and receiver are enabled (ESCI
x
_CR1[TE] = 1, ESCI
x
_CR1[RE] = 1).
c) The data format bit ESCI
x
_CR1[M], is set to 0 (8 data bits), and the parity is disabled
(PE = 0).
d) ESCI
x
_CR1[TIE], ESCI
x
_CR1[TCIE], ESCI
x
_CR1[RIE] interrupt enable bits should be
inactive. Instead, the LIN interrupts should be used.
e) Switch eSCI to LIN mode (ESCI
x
_LCR[LIN] = 1).
f) The LIN standard requires that the break character always be 13 bits long
(ESCI
x
_CR2[BRK13] = 1). The eSCI will work with BRK13=0, but it will violate LIN 2.0.
g) Normally, bit errors should cause the LIN FSM to reset, stop driving the bus immediately, and
stop further DMA requests until the BERR flag has been cleared. Set ESCI
x
_LCR[LDBG] =
0, ESCI
x
_CR2[SBSTP] = 1, and ESCI
x
_CR2[BSTP] = 1 to accomplish these functions.
h) Fast bit error detection provides superior error checking, so ESCI
x
_CR2[FBR] should be set;
normally it will be used with ESCI
x
_CR2[BESM13] = 1.
i) If available, a pulldown should be enabled on the RX input. (Thus if the transceiver fails, the
RX pin will not float).
j) The error indicators NF, FE, BERR, STO, PBERR, CERR, CKERR, and OVFL should be
enabled.
k) Initially a wake-up character may need to be transmitted on the LIN bus, so that the LIN
slaves activate.
Other settings like baud rate, length of break character etc., depend on the LIN slaves to which the eSCI
is connected.
21.5
Revision History
Table 21-22. Changes to MPC5553/5554 for Rev. 4.0 Release
Description of Change
Added this note to the steps for initiating a character transmission:
• “A single 32-bit write to ESCI_CR1 may be used in place of steps b–d above.”
Table 21-23. Changes to MPC5553/5554 for Rev. 5.0 Release
Description of Change
Changed 15 clock cycles to 31 RT clock cycles in the following sections:
• PBERR bit description in Table “ESCIx_SR Field Descriptions”
• PBERR Description
• LIN Error Handling
Summary of Contents for MPC5553
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