Addendum List for Revision 7.1
MPC5607B Reference Manual Errata, Rev. 1
Freescale Semiconductor
8
Chapter 25, FlexCAN,
throughout chapter
Remove references throughout the chapter to “low-cost MCUs.”
Chapter 25, FlexCAN, page
594
Remove Note: above
Table 25-2
:
Note: The individual Rx Mask per Message Buffer feature may not be available in low cost
MCUs. Please consult the specific MCU documentation to find out if this feature is supported.
If not supported, the address range 0x0880-0x097F is considered reserved space,
independent of the value of the BCC bit.
Chapter 25, FlexCAN, page
596
Added this Note in the RTR field description of
Table 25-4 (Message Buffer Structure field
description)
:
Note: Do not configure the last Message Buffer to be the RTR frame.
Chapter 25, FlexCAN, page
619
Remove Note: in
Section 25.4.4.13 Rx Individual Mask Registers (RXIMR0–RXIMR63):
Note: The individual Rx Mask per Message Buffer feature may not be available in low cost
MCUs. Please consult the specific MCU documentation to find out if this feature is supported.
If not supported, the RXGMASK, RX14MASK and RX15MASK registers are available,
regardless of the value of the BCC bit.
Chapter 25, FlexCAN, page
624
Remove Note: at end of
Section 25.5.6, Matching process
:
Note: The individual Rx Mask per Message Buffer feature may not be available in low cost
MCUs. Please consult the specific MCU documentation to find out if this feature is supported.
If not supported, the RXGMASK, RX14MASK, and RX15MASK registers are available,
regardless of the value of the BCC bit.
Chapter 25, FlexCAN, page
629
In
Section 25.5.9.4, Protocol timing
, update the Note following
Figure 25-16 (CAN Engine
Clocking Scheme)
to read: “This clock selection feature may not be available in all MCUs. A
particular MCU may not have a PLL, in which case it would have only the oscillator clock, or
it may use only the PLL clock feeding the FlexCAN module. In these cases, the CLK_SRC bit
in the CTRL Register has no effect on the module operation.”
Chapter 25, FlexCAN, page
631
Update the table title of
Table 25-22
from “CAN Standard Compliant Bit Time Segment Settings”
to “Bosch CAN 2.0B standard compliant bit time segment settings.”
Chapter 25, FlexCAN, page
631
In
Section 25.5.9.4, Protocol timing
, update the Note following
Table 25-22
to read: “Other
combinations of Time Segment 1 and Time Segment 2 can be valid. It is the user’s
responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit
time calculations, use an IPT (Information Processing Time) of 2, which is the value
implemented in the FlexCAN module.”
Chapter 28, Analog-to-Digital
Converter (ADC), page 771
In
Section 28.3.4.2, CTU in trigger mode
, replace the sentence:
If another CTU conversion is triggered before the end of the conversion, that request is
discarded.
with:
If another CTU conversion is triggered before the end of the conversion, that request is
discarded. However, if the CTU has triggered a conversion that is still ongoing on a channel,
it will buffer a second request for the channel and wait for the end of the first conversion before
requesting another conversion. Thus, two conversion requests close together will both be
serviced.
Chapter 28, Analog-to-Digital
Converter (ADC), page 772
In Section
28.3.5.2, Presampling channel enable signals
, in
Table 28-7, Presampling voltage
selection based on PREVALx fields
, in the 01 row, change the “Presampling voltage” field to:
V1 = V
DD_HV_ADC0
or V
DD_HV_ADC1
.
Table 1. MPC5607BRM Rev 7.1 Addenda (continued)
Location
Description
