READI Module
MPC561/MPC563 Reference Manual, Rev. 1.2
24-66
Freescale Semiconductor
•
L-bus data phase error.
•
U-bus address phase error (for a L-bus to U-bus cycle).
•
U-bus data phase error (for a L-bus to U-bus cycle).
L-bus data error conditions are signalled along with the transfer acknowledge for the access. L-bus data
error conditions may occur because of privilege violations, access to protected memory, etc. In such cases,
for a read access, the ERR bit of the UDI is set, and the DV bit in the UDI is reset at the termination of the
access. For a write access, an error public message (TCODE = 8) is transmitted (error code 0b00011).
24.10.6 Exception Sequences
The following cases are defined for sequences of the read/write protocol that differ from those described
in the above sections:
1. If the SC bit is set to start READI read/write accesses, without valid values in the RWAD, then an
L-bus address error may occur, which is handled as described above.
2. If a block access is in progress with all the cycles not yet completed, and the RWA is written to
again, (with or without modifications), then the block access is terminated at the boundary of the
nearest completed access. The resulting data is discarded and not written to the UDI. If a new
access has been programmed in the RWA register, then that access will start once the controller has
recovered.
3. When a block access is in progress with all the cycles not yet completed, writing the SC bit to 0 in
RWA register will terminate the block access and device will send out device ready for
upload/download message.
4. If a any type (single/block) of access is in progress with the cycles not yet completed, and system
reset occurs, the device will send out an error message. The access will be terminated and the SC
bit will be reset. Refer to
5. If any type of (single/block) of access is requested while system is in reset, the device will send out
an error message. The access will not be started and the SC bit will be reset.
24.10.7 Secure Mode
For details refer to
.”
24.10.8 Error Messages
24.10.8.1 Read/Write Access Error
An error message is sent out when an L-bus access error or data error on a write access occurs. The error
code within the error message indicates that an L-bus address or L-bus data error occurred. For other error
handling, see
Section 24.10.5, “Error Handling
.” For a list of error codes, refer to
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
