Burst Buffer Controller 2 Module
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
4-5
The BIU may be programmed for burstable or non-burstable access. If the BIU is programmed for
burstable access, the U-bus address phase transaction is accompanied by the burst request attribute. If
burstable access is allowed by the U-bus slave, the BIU continues current access as burstable, otherwise
current access is executed as a single access. If any protection violation is detected by the IMPU, the
current U-bus access is aborted by the BIU and an exception is signaled to the RCPU.
Show cycle, program trace and debug port access attributes accompanying the RCPU access are forwarded
by the BIU along with the U-bus access.
4.2.1.2
Decompression On Mode
Appendix A, “MPC562/MPC564 Compression Features
” for explanation of the decompression on
mode.
4.2.2
Burst Operation of the BBC
The BBC may initiate and handle burst accesses on the U-bus. The BBCMCR[BE] bit determines whether
the BBC operates burst cycles or not. Burst requests are enabled when the BE bit is set. The BBC handles
non-wrap-around bursts with up to 4 data beats on the internal U-bus.
NOTE
The burst operation in the MPC561/MPC563 is useful if a user system
implements burstable memory devices on the external bus. Otherwise the
mode will cause performance degradation when running code from external
memory.
When the RCPU runs in serialized mode it is recommended that bursts be
disabled by the BBC to speed up MPC561/MPC563 operation.
Burst operation for decompression on and in debug mode is disabled
regardless of BBCMCR[BE] bit setting.
The BBC burst should be turned off if the USIU burst feature is enabled.
4.2.3
Access Violation Detection
Instruction memory protection is assigned on a regional basis. Default operation of IMPU is done on a
global region. The IMPU has control registers which contain the following information: region protection
on/off, region base address, size and access permissions.
Protection logic is activated only if the RCPU MSR[IR] bit is set.
During each fetch request from the RCPU core to instruction memory, the address is compared to a value
in the region base address of enabled regions. Any address matching the specific region within its
appropriate size as defined in the region attribute register sets a match indication.
When more than one match indication occurs, the effective region is the region with the highest priority.
Priority is determined by region number. The lowest region number has the highest priority and the global
region has lowest priority.
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
