Memory Controller
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-23
Note:
Timing in this table refers to the typical timing only. Consult the electrical characteristics for exact worst-case timing values.
1/4 clock actually means 0 to 1/4 clock, 1/2 clock means 1/4 to 1/2 clock.
Additional timing rules not covered in
include the following:
•
If SETA = 1, an external TA signal is required to terminate the cycle.
•
If TRLX = 1 and SETA = 1, the minimum cycle length = 3 clock cycles (even if SCY = 0000)
•
If TRLX = 1, the number of wait states = 2
∗
SCY & 2
∗
BSCY
•
ACS = 01 is not defined (reserved).
•
If EHTR = 1, an extra (idle) clock cycle is inserted between a read cycle and a following read cycle
to another region, or between a read cycle and a following write cycle to any region.
•
If LBDIP = 1 (late BDIP assertion), the BDIP signal is asserted only after the number of wait states
for the first beat in a burst have elapsed. See
in
Chapter 9, “External Bus Interface
Section 9.5.5, “Burst Mechanism
.”
NOTE
The LBDIP/TBDIP function can operate only when the cycle termination is
internal, using the number of wait states programmed in one of the OR
x
registers. The LBDIP/TBDIP function cannot be activated at the same
time—results are unknown.
0
write
11
1
1/2 * clock
1/2 * clock
3/4 * clock
1/2 * clock
X
2 + SCY
1
read
00
X
0
1/4 * clock
3/4 clock
X
1/4 * clock
2 +
2 * SCY
1
read
10
X
(1 + 1/4) *
clock
1/4 * clock
(1 + 3/4) *
clock
X
1/4 * clock
3 +
2 * SCY
1
read
11
X
(1 + 1/2) *
clock
1/4 * clock
(1 + 3/4) *
clock
X
1/4 * clock
3 +
2 * SCY
1
write
00
0
0
1/4 * clock
3/4 clock
1/4 * clock
X
2 +
2 * SCY
1
write
10
0
(1 + 1/4) *
clock
1/4 * clock
(1 + 3/4) *
clock
1/4 * clock
X
3 +
2 * SCY
1
write
11
0
(1 + 1/2) *
clock
1/4 * clock
(1 + 3/4)
clock
1/4 * clock
X
3 +
2 * SCY
1
write
00
1
0
1/4 * clock
3/4 clock
(1 + 1/2) *
clock
X
3 +
2 * SCY
1
write
10
1
(1 + 1/4) *
clock
(1 + 1/2) *
clock
(1 + 3/4)
clock
(1 + 1/2) *
clock
X
4 +
2 * SCY
1
write
11
1
(1 + 1/2) *
clock
(1 + 1/2) *
clock
(1 + 3/4)
clock
(1 + 1/2) *
clock
X
4 +
2 * SCY
Table 10-3. Programming Rules for Timing Strobes (continued)
TRLX
Access
Type
ACS
CSNT
Address
to CS
Asserted
CS
Negated to
Add/Data
Invalid
Address to
WE/BE or
OE
Asserted
WE/BE
Negated to
Add/Data
Invalid
OE
Negated to
Add/Data
Invalid
Total
Number of
Cycles
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
