Memory Controller
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
10-27
dual mapped address, and the cycle type matches AT/ATM field in DMBR/DMOR register, then the
following occur:
•
The chip-select that is mapped to the access does not respond to that address (it remains negated)
•
The chip-select region selected is determined by the DMCS bit field in the DMBR register
•
The attributes for the access are taken from the corresponding chip select region
Dual mapping can only be enabled over memory addresses in the range 0x0000 0000 through 0x000F
FFFF.
NOTE
Internal Flash must be disabled to use dual mapping over an external
memory.
10.7
Global (Boot) Chip-Select Operation
Global (boot) chip-select operation allows address decoding for a boot ROM before system initialization.
If the global chip-select feature is enabled then the memory controller is enabled from reset.
The global chip select port size is programmable at system reset using RCW[BPS]. The global chip select
does not provide write protection and responds to all address types, allowing a boot ROM to be located
anywhere in the address space.
The memory controller will operate in this boot mode until the first write to any chip select option register
(ORx).The chip select signal can be programmed to continue decoding a range of addresses after this write,
provided the preferred address range is first loaded into the chip select base register (BRx). After the first
write to ORx, the global chip select can only be restarted with a system reset.
Which chip-select line is used as the global chip select, and how it operates, is determined by the reset
configuration parameters:
•
FLEN – Internal Flash enable (bit 20)
•
BDIS – Boot disable (bit 3)
•
DME – Dual mapping enable (bit 31)
summarizes global chip select operations for all combinations of values on these reset
configuration word lines.In case 1, where FLEN, BDIS, DME = 0b000 (all cleared) at reset, CS0 is the
global chip-select output. When the RCPU begins accessing memory after system reset, CS0 is asserted
for every address, for accesses to both internal and external instructions and data.
In case 2, where FLEN, BDIS, DME = 0b001 at reset, CS0 is asserted for all external address accesses
(instructions and data) and for internal instruction accesses. However, CS3 is asserted for all internal data
accesses. CS3 is used in this case to allow dual mapping of loads/stores to/from an alternative bank which
is not the memory bank normally used for instructions/data. In this way CS3 can be used to allow
load/store from a different memory bank from reset. DME can then be disabled as required.
The global chip select feature is disabled by driving only the BDIS line of the RCW (FLEN, BDIS,
DME = 0b010). This is shown in case 3 of
shows the initial values of the “boot bank” in the memory controller.
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
