CAN 2.0B Controller Module
MPC561/MPC563 Reference Manual, Rev. 1.2
16-10
Freescale Semiconductor
16.3.3.1
Configuring the TouCAN Bit Timing
The following considerations must be observed when programming bit timing functions.
•
If the programmed PRESDIV value results in a single system clock per one time quantum, then the
PSEG2 field in CANCTRL2 register must not be programmed to zero.
•
If the programmed PRESDIV value results in a single system clock per one time quantum, then the
information processing time (IPT) equals three time quanta; otherwise it equals two time quanta.
If PSEG2 equals two, then the TouCAN transmits one time quantum late relative to the scheduled
sync segment.
•
If the prescaler and bit timing control fields are programmed to values that result in fewer than 10
system clock periods per CAN bit time and the CAN bus loading is 100%, then any time the rising
edge of a start-of-frame (SOF) symbol transmitted by another node occurs during the third bit of
the intermission between messages, the TouCAN may not be able to prepare a message buffer for
transmission in time to begin its own transmission and arbitrate against the message which
transmitted the early SOF.
•
The TouCAN bit time must be programmed to be greater than or equal to nine system clocks, or
correct operation is not guaranteed.The duration of the synchronization segment, SYNC_SEG, is
not programmable and is fixed at one time quantum.
16.3.4
Error Counters
The TouCAN has two error counters, the transmit (Tx) error counter and the receive (Rx) error counter.
Refer to
Section 16.7, “Programming Model
,” for more information on error counters. The rules for
increasing and decreasing these counters are described in the CAN protocol, and are fully implemented in
the TouCAN. Each counter has the following features:
•
Eight-bit up/down-counter
•
Increment by eight (Rx error counter also increments by one)
•
Decrement by one
•
Avoid decrement when equal to zero
•
Rx error counter reset to a value between 119 and 127 inclusive, when the TouCAN transitions
from error passive to error active
16
0.500
1, 2
2, 4
16, 8
56
0.125
1, 2
8, 16
56, 28
40
0.125
1, 2
8, 16
40, 20
25
0.125
1, 1.25, 2.5
8,10, 20
25, 20,10
20
0.125
1, 2, 2.5
8, 16, 20
20, 10, 8
16
0.125
1, 2
8,16
16, 8
Table 16-8. Example System Clock, CAN Bit Rate, and S-Clock Frequencies (continued)
System Clock
Frequency
(MHz)
CAN Bit Rate
(MHz)
Possible S-Clock
Frequency (MHz)
Possible Number of
Time Quanta/Bit
PRESDIV Value + 1
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
