CAN 2.0B Controller Module
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-21
Figure 16-7. Interrupt Levels on IRQ with ILBS
16.7
Programming Model
shows the TouCAN address map. The lowercase “x” appended to each register name
represents “A”, “B” or “C” for the TouCAN_A, TouCAN_B, or TouCAN_C module, respectively. Refer
to
to locate each TouCAN module in the MPC561/MPC563 address map.
The column labeled “Access” indicates the privilege level at which the CPU must be operating to access
the register. A designation of “S” indicates that supervisor mode is required. A designation of “S/U”
indicates that the register can be programmed for either supervisor mode access or unrestricted access.
The address space for each TouCAN module is split, with 128 bytes starting at the base address, and an
extra 256 bytes starting at the base a128. The upper 256 are fully used for the message buffer
structures. Of the lower 128 bytes, some are not used. Registers with bits marked as “reserved” should
always be written as logic 0.
Typically, the TouCAN control registers are programmed during system initialization, before the TouCAN
becomes synchronized with the CAN bus. The configuration registers can be changed after
synchronization by halting the TouCAN module. This is done by setting the HALT bit in the TouCAN
module configuration register (CANMCR). The TouCAN responds by asserting CANMCR[NOTRDY].
Additionally, the control registers can be modified while the MCU is in background debug mode.
NOTE
The TouCAN has no hard-wired protection against invalid bit/field
programming within its registers. Specifically, no protection is provided if
the programming does not meet CAN protocol requirements.
Table 16-10. TouCAN Register Map
Access
Address
MSB
0
LSB
15
S
0x30 7080(A)
0x30 7480(B)
0x30 7880(C)
TouCAN Module Configuration Register (CANMCR_x)
for bit descriptions.
S
0x30 7082(A)
0x30 7482(B)
0x30 7882(C)
TouCAN Test Register (CANTCR_x)
.
IMB3 CLOCK
ILBS [1:0]
IMB3 IRQ [7:0]
IRQ
7:0
00
01
11
10
IRQ
15:8
IRQ
23:16
IRQ
31:24
IRQ
7:0
00
01
11
10
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
