Development Support
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
23-29
23.4.2
Development Serial Clock
The development serial clock (DSCK) is used to shift data into and out of the development port shift
register. At the same time, the new most significant bit of the shift register is presented at the DSDO pin.
In all further discussions references to the DSCK signal imply the internal synchronized value of the clock.
The DSCK input must be driven either high or low at all times and not allowed to float. A typical target
environment would pull this input low with a resistor.
The clock may be implemented as a free running clock or as gated clock. As discussed in section
Section 23.4.6.5, “Development Port Serial Communications — Trap Enable Mode
” and section
Section 23.4.6.8, “Development Port Serial Communications — Debug Mode
,” the shifting of data is
controlled by ready and start signals so the clock does not need to be gated with the serial transmissions.
The DSCK pin is also used at reset to enable debug mode and immediately following reset to optionally
cause immediate entry into debug mode following reset.
23.4.3
Development Serial Data In
Data to be transferred into the development port shift register is presented at the development serial data
in (DSDI) pin by external logic. To be sure that the correct value is used internally. When driven
asynchronous (synchronous) with the system clock, the data presented to DSDI must be stable a setup time
before the rising edge of DSCK (CLKOUT) and a hold time after the rising edge of DSCK (CLKOUT).
The DSDI pin is also used at reset to control the overall chip configuration mode and to determine the
development port clock mode. See section
Section 23.4.6.4, “Development Port Serial Communications
” for more information.
23.4.4
Development Serial Data Out
The debug mode logic shifts data out of the development port shift register using the development serial
data out (DSDO) pin. All transitions on DSDO are synchronous with DSCK or CLKOUT depending on
the clock mode. Data will be valid a setup time before the rising edge of the clock and will remain valid a
hold time after the rising edge of the clock.
Refer to
for DSDO data meaning.
23.4.5
Freeze Signal
The freeze indication means that the processor is in debug mode (i.e., normal processor execution of user
code is frozen). On the MPC561/MPC563, the freeze state can be indicated by three different pins. The
FRZ signal is generated synchronously with the system clock. This indication may be used to halt any
off-chip device while in debug mode as well as a handshake means between the debug tool and the debug
port. The internal freeze status can also be monitored through status in the data shifted out of the debug
port.
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
