IEEE 1149.1-Compliant Interface (JTAG)
MPC561/MPC563 Reference Manual, Rev. 1.2
25-2
Freescale Semiconductor
The TAP consists of five dedicated signal pins, a 16-state TAP controller, and two test data registers. A
boundary scan register links all device signal pins into a single shift register. The test logic implemented
utilizes static logic design. The MPC561/MPC563 implementation provides the capability to:
1. Perform boundary scan operations to test circuit-board electrical continuity.
2. Bypass the MPC561/MPC563 for a given circuit-board test by effectively reducing the boundary
scan register to a single cell.
3. Sample the MPC561/MPC563 system pins during operation and transparently shift out the result
in the boundary scan register.
4. Disable the output drive to pins during circuit-board testing.
NOTE
Certain precautions must be observed to ensure that the IEEE 1149-like test
logic does not interfere with nontest operation. JCOMP must be low prior to
PORESET assertion after low power mode exits, otherwise an unknown
state will occur.
25.1.1
Overview
An overview of the MPC561/MPC563 scan chain implementation is shown in
. The
MPC561/MPC563 implementation includes a TAP controller, a 4-bit instruction register, and two test
registers (a one-bit bypass register and a 427-bit (MPC563) or 423-bit (MPC561) boundary scan register).
This implementation includes a dedicated TAP consisting of the following signals:
•
TCK — a test clock input to synchronize the test logic. (with an internal pull-down resistor)
•
TMS — a test mode select input (with an internal pullup resistor) that is sampled on the rising edge
of TCK to sequence the TAP controller’s state machine.
•
TDI — a test data input (with an internal pullup resistor) that is sampled on the rising edge of TCK.
•
TDO — a three-state test data output that is actively driven in the shift-IR and shift-DR controller
states. TDO changes on the falling edge of TCK. (This pin also has a weak pull-up that is active
when output drivers are disabled, except during a HI-Z instruction).
•
TRST — an asynchronous reset with an internal pull-up resistor that provides initialization of the
TAP controller and other logic required by the standard. This input is multiplexed with the
PORESET signal.
•
JCOMP — JTAG Compliancy – This signal provides JTAG IEEE1149.1 compatibility and selects
between normal operation (low) and JTAG test mode (high).
NOTE
JTAG mode does not provide access to the internal MPC561/MPC563
circuitry. It allows access only to the input or output pad (periphery)
circuitry.
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
