66-MHz Electrical Characteristics
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
G-25
NOTE
The D[0:31] input timings 17 and 18 refer to the rising edge of the CLKOUT
in which the TA input signal is asserted.
Figure G-10. CLKOUT Pin Timing
27d
WE[0:3]/BE[0:3] negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’1’, CSNT = '1’.
CS negated to ADDR[8:31] Invalid
-GPCM- write access, TRLX=’1’, CSNT = '1’, ACS = 10,ACS = =’11’,
EBDF = 1
14.65
—
ns
28
ADDR[8:31], TSIZ[0:1], RD/WR, BURST, valid to CLKOUT Rising
Edge. (Slave mode Setup Time)
3.5
—
ns
28a
Slave Mode D[0:31] valid to CLKOUT Rising Edge
3.7
—
ns
29
TS valid to CLKOUT Rising Edge (Setup Time)
2
—
ns
30
CLKOUT Rising Edge to TS Valid (Hold Time).
3.6
—
ns
1
The timing for BR output is relevant when the deviceMPC561/MPC563 is selected to work with external bus
arbiter. The timing for BG output is relevant when the MPC561/MPC563 is selected to work with internal bus
arbiter.
2
The setup times required for TA, TEA, and BI are relevant only when they are supplied by the external device
(and not the memory controller).
3
The maximum value of spec 8 for DATA[0:31] pins must be extended by 1.1 ns if the pins have been precharged
to greater than V
DDL
. This is the case if an external slave device on the bus is running at the max. value of
VDATAPC. This is currently specified at 3.1 V. The 1.1 ns addition to spec 8 reflects the expected timing
degradation for 3.1 V.
4
The device may be used without limitation in conjuction with 2.6 V external memories. Pre-discharge function
is not available for 66-MHz operation.
5
The timing 27 refers to CS when ACS = ‘00’ and to WE[0:3]/BE[0:3] when CSNT = ‘0’.
Table G-10. Bus Operation Timing (continued)
Note:
(V
DD
= 2.6 V
±
0.1 V, V
DDH
= 5.0 V
±
0.25 V, T
A
= T
L
to T
H
, 50 pF load unless noted otherwise)
Characteristic
66 MHz
Uni
t
Min
Max
1
3
2
4
5
CLKOUT
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
