MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
5-1
Chapter 5
Unified System Interface Unit (USIU) Overview
The unified system interface unit (USIU) of the MPC561/MPC563 consists of several functional modules
that control system start-up, system initialization and operation, system protection, and the external system
bus. The MPC561/MPC563 USIU functions include the following and are discussed in the designated
chapters:
•
System configuration and protection with GPIO capability and an enhanced interrupt controller.
Refer to
Chapter 6, “System Configuration and Protection
•
System reset monitoring and generation, refer to
.”
•
Clock synthesis, power management, and debug support. Refer to
•
External bus interface (EBI), refer to
Chapter 9, “External Bus Interface
•
Memory controller that supports four memory banks. Refer to
Chapter 10, “Memory Controller
.”
The USIU provides system configuration and protection features that control the overall system
configuration and supply various monitors and timers including the bus monitor, software watchdog timer,
periodic interrupt timer, decrementer, time base, and real-time clock. Freeze support and low power stop
is provided. The interrupt controller supports up to eight external interrupts, eight levels for all internal
USIU interrupt sources and 32 levels for internal peripheral modules on the IMB bus. It has an enhanced
mode of operation, which simplifies the MPC561/MPC563 interrupt structure and speeds up interrupt
processing.
Additionally, the USIU provides several pinout configurations that allow up to 64 general-purpose I/O,
external 32-bit port that supports internal and external masters, and various debug functions.
Reset logic for the MPC561/MPC563 provides soft and hard resets, checkstop and watchdog resets, and
other types of reset. The reset status register (RSR) reflects the most recent source to cause a reset.
The clock synthesizer generates the clock signals used by the USIU as well as the other modules and
external devices. This circuitry can generate a system clock from a range of crystals, typically in the 4 MHz
or 20 MHz range.
The USIU supports various low-power modes. Each one supplies a different range of power consumption,
functionality and wake-up time. Refer to
Chapter 8, “Clocks and Power Control
,” for details.
The EBI handles the transfer of information between the internal busses and the memory or peripherals in
the external address space. The MPC561/MPC563 is designed to allow external bus masters to request and
obtain mastership of the system bus, and if required access the on-chip memory and registers. Refer to
Chapter 9, “External Bus Interface
,” for details.
The memory controller module provides glueless interface to many types of memory devices and
peripherals. It supports up to four memory banks. Refer to
Chapter 10, “Memory Controller
for details.
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
