Reset
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
7-3
use the MPC561/MPC563 CLKOUT signal. This source of reset can be optionally asserted if the LOLRE
bit in the PLL, low-power, and reset control register (PLPRCR) is set. The enabled PLL loss of lock event
generates an internal hard reset sequence. Refer to
Chapter 8, “Clocks and Power Control
,” for more
information on loss of PLL lock.
7.1.5
On-Chip Clock Switch
If the system clock is switched to the backup clock or switched from backup clock to another clock source
an internal hard reset sequence is generated. Refer to
Chapter 8, “Clocks and Power Control
.”
7.1.6
Software Watchdog Reset
When the MPC561/MPC563 software watchdog counts to zero, a software watchdog reset is asserted. The
enabled software watchdog event generates an internal hard reset sequence.
7.1.7
Checkstop Reset
When the RCPU enters a checkstop state, and the checkstop reset is enabled (the CSR bit in the PLPRCR
is set), a checkstop reset is asserted. The enabled checkstop event generates an internal hard reset sequence.
Refer to the
RCPU Reference Manual
for more information.
7.1.8
Debug Port Hard Reset
When the development port receives a hard reset request from the development tool, an internal hard reset
sequence is generated. In this case the development tool must reconfigure the debug port. Refer to
Chapter 23, “Development Support
,” for more information.
7.1.9
Debug Port Soft Reset
When the development port receives a soft reset request from the development tool, an internal soft reset
sequence is generated. In this case the development tool must reconfigure the debug port. Refer to
Chapter 23, “Development Support
,” for more information.
7.1.10
JTAG Reset
When the JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated. Refer
to
Chapter 25, “IEEE 1149.1-Compliant Interface (JTAG)
,” for more information.
7.1.11
ILBC Illegal Bit Change
When locked bits in the PLPRCR register are changed, an internal hard reset sequence is generated. Refer
to
Chapter 8, “Clocks and Power Control
.”
7.2
Reset Actions Summary
summarizes the action taken for each reset.
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
