Clocks and Power Control
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-5
If limp mode is enabled (by the MODCK[1:3] pins), and PORESET is negated before the external
oscillator has started up, the backup clock, BUCLK, will be used to clock the device. The device will start
to run in limp mode. Software can then switch the clock mode from BUCLK to PLL. If an application
requires that the device always comes out of reset in normal mode, PORESET should be asserted long
enough for the external oscillator to start up. The maximum start-up time of an external oscillator is given
in
Appendix F, “Electrical Characteristics
” and PORESET should be asserted for this time and at least an
additional 100, 000 input clock cycles.
If limp mode is disabled at reset, a short reset of at least 3 µs is enough to obtain normal chip operation,
because the BUCLK will not start. The system will wait for the external oscillator to start-up and stabilize.
The PLL will begin to lock once PORESET has been negated, assuming stable KAPWR and VDDSYN
power supplies and internal oscillator (or external clock). The PLL maximum lock time is determined by
the input clock to the phase comparator. The PLL locks within 500 input clock cycles if the PLPRCR[MF]
<= 4. The PLL locks within 1000 input clock cycles if PLPRCR[MF] >4. HRESET will be released 512
system clock cycles after the PLL locks.
Whenever PORESET is asserted, the MF bits are set according to
, and the division factor high
frequency (DFNH) and division factor low frequency (DFNL) bits in SCCR are set to the value of 0 (
÷
1
for DFNH and
÷
2 for DFNL).
Figure 8-3. System PLL Block Diagram
8.2.5
PLL Pins
The following pins are dedicated to the PLL operation:
•
VDDSYN — Drain voltage. This is the V
DD
dedicated to the analog PLL circuits. The voltage
should be well-regulated and the pin should be provided with an extremely low impedance path to
the V
DD
power rail. VDDSYN should be bypassed to VSSSYN by a 0.1 µF capacitor located as
close as possible to the chip package.
•
VSSSYN — Source voltage. This is the V
SS
dedicated to the analog PLL circuits. The pin should
be provided with an extremely low impedance path to ground. VSSSYN should be bypassed to
VDDSYN by a 0.1 µF capacitor located as close as possible to the chip package.
Phase
Comparator
Multiplication Factor
MF[0:11]
XFC
OSCCLK
Up
Down
VCOOUT
Feedback
Clock
Delay
Charge
Pump
VCO
Division Factor
DIVF[0:4]
VSSSYN
VDDSYN
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
