Clocks and Power Control
MPC561/MPC563 Reference Manual, Rev. 1.2
8-28
Freescale Semiconductor
During the power down sequence PORESET needs to be asserted while VDD, NVDDL, and QVDDL are
at a voltage greater than or equal to 2.5 V. Below this voltage the power supply chip can be turned off.
If the turn-off voltage of the power supply chip is greater than 0.74 V for the 2.6-V supply and greater than
0.8 V for the 5-V supply, then the circuitry inside the MPC561/MPC563 will act as a load to the respective
supply and will discharge the supply line down to these values. Since the 2.6-V logic represents a larger
load to the supply chip, the 2.6-V supply line will decay faster than the 5-V supply line.
Figure 8-14. No Standby, No KAPWR, All System Power-On/Off
Power On
Power Off
Operating
See Note 1. See Note 2.
VDDH
VDD, NVVL,
KAPWR
IRAMSTBY
VDDA, VRH
VDDSYN
VFLASH (5 V)
PORESET
HRESET
QVDDL
1
VDDH
≥
QVDDL - 0.5 V
VDDA can lag VDDH, and VDDSYN can lag QVDDL, but both must be at a valid level before resets are negated.
2
If keep-alive functions are NOT used, then when system power is on: KAPWR = QVDDL ± 0.1 V; KAPWR
≤
2.7 V
3
If keep-alive functions ARE used, then KAPWR = QVDDL = NVDDL = 2.6 V ± 0.1 V when system power is on
KAPWR = 2.6 V ± 0.1 V when system power is off. IRAMSTBY should be powered prior to the other supplies. If
IRAMSTBY is powered at the same time as the other supplies, it should be allowed to stabilize before PORESET
is negated. Normal system power is defined as QVDDL = VDD = VDDF = VDDSYN = KAPWR = 2.6 ± 0.1 V and
VDDA = VDDH = VFLASH = 5.0 ± 0.25 V. Flash programming requirements are the same as normal system
power. VFLASH should always be 5.0 ± 0.25 V. Note: Flash is not implemented on the MPC561.
4
Do not hold the 2.6-V supplies at ground while VDDH/VDDA is ramping to 5 V.
5
If 5 V is applied before the 2.6-V supply, all 5-V outputs will be in indeterminate states until the 2.6-V supply
reaches a level that allows reset to be distributed throughout the device If 5 V is applied before the 2.6-V supply,
all 5-V outputs will be in indeterminate states until the 2.6-V supply reaches a level that allows reset to be
distributed throughout the device
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...