Clocks and Power Control
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
8-33
8.11.2
PLL, Low-Power, and Reset-Control Register (PLPRCR)
The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered by the keep-alive
power supply.
24
—
Reserved
25:27
DFNL[0:2]
Division factor low frequency. The user can load these bits with the desired divide value
and the CSRC bit to change the frequency. Changing the value of these bits does not result
in a loss of lock condition. These bits are cleared by power-on or hard reset. Refer to
Section 8.5.1, “General System Clocks
” and
for details on using these bits.
000 Divide by 2
001 Divide by 4
010 Divide by 8
011 Divide by 16
100 Divide by 32
101 Divide by 64
110 Reserved
111 Divide by 256
28
—
Reserved
29:31
DFNH
Division factor high frequency. These bits determine the general system clock frequency
during normal mode. Changing the value of these bits does not result in a loss of lock
condition. These bits are cleared by power-on or hard reset. The user can load these bits
at any time to change the general system clock rate. Note that the GCLKs generated by
this division factor are not 50% duty cycle (i.e. CLKOUT).
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Reserved
Table 8-10. COM and CQDS Bits Functionality
COM[0:1] CQDS
Function
00
x
Clock Output Enabled Full-Strength Output Buffer, Bus pins full
drive
01
0
Clock Output Enabled Half-Strength Output Buffer, Bus pins
reduced drive
01
1
Clock Output Enabled Quarter-Strength Output Buffer, Bus pins
reduced drive
10
x
Clock Output Disabled, Bus pins full drive
11
x
Clock Output Disabled, Bus pins reduced drive
Table 8-9. SCCR Bit Descriptions (continued)
Bits
Name
Description
Summary of Contents for MPC561
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