External Bus Interface
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-29
Figure 9-21. Non-Wrap Burst with One Data Beat
9.5.6
Alignment and Packaging of Transfers
The MPC561/MPC563 external bus requires natural address alignment:
•
Byte accesses allow any address alignment
•
Half-word accesses require address bit 31 to equal zero
CLKOUT
ADDR[0:29]
TS
BR
BG
BB
Data
TA
RD/
WR
BURST
TSIZ[0:1]
BDIP
DATA
is Sampled
First and Last Beat
00
ADDR[30:31]
00
n (n modulo 4 = 3)
Is Never Asserted
O
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...