Memory Controller
MPC561/MPC563 Reference Manual, Rev. 1.2
10-24
Freescale Semiconductor
10.4
Write and Byte Enable Signals
The GPCM determines the timing and value of the WE/BE signals if allowed by the port size of the
accessed bank, the transfer size of the transaction and the address accessed.
The functionality of the WE/BE[0:3] signals depends upon the value of the write enable/byte select
(WEBS) bit in the corresponding BR register. Setting WEBS to 1 will enable these signals as BE, while
clearing it to zero will enable them as WE. WE is asserted only during write access, while BE is asserted
for both read and write accesses. The timing of the WE/BE signals remains the same in either case, and is
determined by the TRLX, ACS and CSNT bits.
The upper WE/BE (WE0/BE0) indicates that the upper eight bits of the data bus (D0–D7) contains valid
data during a write/read cycle. The upper-middle write byte enable (WE1/BE1) indicates that the
upper-middle eight bits of the data bus (D8–D15) contains valid data during a write/read cycle. The
lower-middle write byte enable (WE2/BE2) indicates that the lower-middle eight bits of the data bus
(D16–D23) contains valid data during a write/read cycle. The lower write/read enable (WE3/BE3)
indicates that the lower eight bits of the data bus contains valid data during a write cycle.
The write/byte enable lines affected in a transaction for 32-bit port (PS = 00), a 16-bit port (PS = 10) and
a 8-bit port (PS = 01) are shown in
10.5
Dual Mapping of the Internal Flash EEPROM Array
The internal Flash EEPROM (UC3F) module can be mapped to an external memory region controlled by
the memory controller. Only one region can be programmed to be dual-mapped. When dual mapping is
enabled (DME bit is set in the DMBR register) and when an internal address matches the dual-mapped
address range (as programmed in the DMBR) with the cycle type matching the AT/ATM field in
DMBR/DMOR registers, the following occurs:
•
The internal Flash memory does not respond to that address
•
The memory controller takes control of the external access
Table 10-4. Write Enable/Byte Enable Signals Function
1
1
This table shows which write enables are asserted (indicated with an ‘X’) for different combinations of port size and
transfer size.
Transfer
Size
TSIZ
Address
32-bit Port Size
16-bit Port Size
8-bit Port Size
A30 A31
WE0/
BE0
WE1/
BE1
WE2
BE2
WE3/
BE3
WE0/
BE0
WE1/
BE1
WE2/
BE2
WE3/
BE3
WE0
/
BE0
WE1
/BE1
WE
2
BE2
WE3/
BE3
Byte
0
1
0
0
X
X
X
0
1
0
1
X
X
X
0
1
1
0
X
X
X
0
1
1
1
X
X
X
Half-
Word
1
0
0
0
X
X
X
X
X
1
0
1
0
X
X
X
X
X
Word
0
0
0
0
X
X
X
X
X
X
X
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
