L-Bus to U-Bus Interface (L2U)
MPC561/MPC563 Reference Manual, Rev. 1.2
11-6
Freescale Semiconductor
When the access by the RCPU is not permitted, the L2U module asserts a data memory storage exception
to the RCPU.
For speculative load/store accesses from the RCPU to a region marked as guarded (G bit of region attribute
register is set), the L2U asks the RCPU to retry the L-bus cycle until either the access is not speculative,
or is canceled by the RCPU.
In the case of attempted accesses to a guarded region together with any other protection violation (no
access), the L2U retries the access. The L2U handles this event as a data storage violation only when the
access becomes non-speculative.
Note that access protection is active only when the MPC500’s MSR[DR] = 1. When MSR[DR] = 0, DMPU
exceptions are disabled, all accesses are considered to be to a guarded memory area, and no speculative
accesses are allowed. In this case, if the L-bus master [RCPU] initiates a non-CALRAM cycle (access
through the L2U) that is marked speculative, the L2U asks the RCPU to retry the L-bus cycle until either
the access is not speculative, or it is canceled by the RCPU Core.
NOTE
The programmer must not overlap the CALRAM memory space with any
enabled region. Overlapping an enabled region with CALRAM memory
space disables the L2U data memory protection for that region.
If an enabled region overlaps with the L-bus space, the DMPU ignores all
accesses to addresses within the L-bus space. If an enabled region overlaps
with MPC500 register addresses, the DMPU ignores any access marked as
an MPC500 access.
11.5.2
Associated Registers
shows registers that are used to control the DMPU of the L2U module. All the registers are
special purpose registers that are accessed via the MPC500 mtspr/mfspr instructions. The registers are also
accessed by an external master when EMCR[CONT] = 0. See
Section 11.8, “L2U Programming Model
,”
for register diagrams and bit descriptions.
.
Table 11-1. DMPU Registers
Name
Description
L2U_RBA0
Region Base Address Register 0
L2U_RBA1
Region Base Address Register 1
L2U_RBA2
Region Base Address Register 2
L2U_RBA3
Region Base Address Register 3
L2U_RA0
Region Attribute Register 0
L2U_RA1
Region Attribute Register 1
L2U_RA2
Region Attribute Register 2
L2U_RA3
Region Attribute Register 3
L2U_GRA
Global Region Attribute
Summary of Contents for MPC561
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Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
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Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
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Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
