QADC64E Legacy Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-9
13.3.1.1
Low Power Stop Mode
When the STOP bit in the QADCMCR is set, the QADC64E clock (QCLK) which clocks the A/D
converter, is disabled and the analog circuitry is powered down. This results in a static, low power
consumption, idle condition. The stop mode aborts any conversion sequence in progress. Because the bias
currents to the analog circuits are turned off in stop mode, the QADC64E requires some recovery time (T
SR
in
Appendix F, “Electrical Characteristics
”) to stabilize the analog circuits after the stop enable bit is
cleared.
In stop mode:
•
BIU state machine and logic do not shut down
•
The CCW and result is not reset and is not accessible
•
The module configuration register (QADCMCR), the interrupt register (QADCINT), and the test
register (QADCTEST) are fully accessible and are not reset
•
The data direction register (DDRQA), port data register (PORTQA/PORTQB), and control register
0 (QACR0) are not reset and are read-only accessible
•
Control register 1 (QACR1), control register 2 (QACR2), and the status registers (QASR0 and
QASR1) are reset and are read-only accessible
•
In addition, the periodic/interval timer is held in reset during stop mode
If the STOP bit is clear, stop mode is disabled.
13.3.1.2
Freeze Mode
Freeze mode occurs when the background debug mode is enabled in the USIU and a breakpoint is
encountered. This is indicated by the assertion of the internal FREEZE line on the IMB3. The FRZ bit in
the QADCMCR determines whether or not the QADC64E responds to an IMB3 internal FREEZE signal
assertion. Freeze is very useful when debugging an application.
When the internal FREEZE signal is asserted and the FRZ bit is set, the QADC64E finishes any conversion
in progress and then freezes.
Depending on when the FREEZE signal is asserted, there are three possible queue "freeze" scenarios:
•
When a queue is not executing, the QADC64E freezes immediately
•
When a queue is executing, the QADC64E completes the conversion in progress and then freezes
8
SUPV
Supervisor/Unrestricted Data Space. Refer to
Section 13.3.1.4, “Supervisor/Unrestricted
for more information.
0 = Only the module configuration register, test register, and interrupt register are designated as
supervisor-only data space. Access to all other locations is unrestricted.
1 = All QADC64E registers and CCW/result tables are designated as supervisor-only data space.
9:15
—
Reserved. Write as zeros.
Table 13-5. QADCMCR Bit Descriptions (continued)
Bits
Name
Description
Summary of Contents for MPC561
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