QADC64E Legacy Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
13-11
access mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user data space accesses. The SUPV bit in the QADCMCR designates the assignable
space as supervisor or unrestricted.
The following information applies to accesses to address space located within the module’s 16-bit
boundaries and where the response is a bus error. See
for more information.
•
Attempts to read a supervisor-only data space when not in the supervisor access mode and
SUPV = 1, causes the bus master to assert a bus error condition. No data is returned. If SUPV = 0,
the QADC64E asserts a bus error condition and no data is returned.
•
Attempts to write to supervisor-only data space when not in the supervisor access mode and
SUPV = 1, causes the bus master to assert a bus error condition. No data is written. If SUPV = 0,
the QADC64E asserts a bus error condition and the register is not written.
•
Attempts to read unimplemented data space in the unrestricted access mode and SUPV = 1, causes
the bus master to assert a bus error condition and no data is returned. In all other attempts to read
unimplemented data space, the QADC64E causes a bus error condition and no data is returned.
•
Attempts to write unimplemented data space in the unrestricted access mode and SUPV = 1, causes
the bus master to assert a bus error condition and no data is written. In all other attempts to write
unimplemented data space, the QADC64E causes a bus error condition and no data is written.
•
Attempts to read assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and no data
is returned.
•
Attempts to write assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and the
register is not written.
The bus master indicates the supervisor and user space access with the function code bits (FC[2:0]) on the
IMB3. For privilege violations, refer to the
Chapter 9, “External Bus Interface
” to determine the
consequence of a bus error cycle termination.
Table 13-6. QADC64E Bus Error Response
S/U
1
Mode
1
S/U = Supervisor/Unrestricted
SUPV Bit
Supervisor-Only
Register
Supervisor/
Unrestricted Register
Reserved/
Unimplemented
Register
U
0
QADC64E bus error
2
2
QADC64E bus error = Caused by QADC64E
Valid access
4
QADC64E bus error
2
U
1
Master bus error
3
3
Master bus error = Caused by bus master
4 Access to QADCTEST register will act as a reserved/unimplemented register unless in factory
test mode
Master bus error
3
Master bus error
3
S
0
Valid access
Valid access
QADC64E bus error
2
S
1
Valid access
Valid access
QADC64E bus error
2
Summary of Contents for MPC561
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Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
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Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
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