QADC64E Legacy Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
13-14
Freescale Semiconductor
13.3.4
Port Data Direction Register (DDRQA)
The port data direction register, DDRQA, is associated with port A digital input/output signals only. Any
bit set in this register configures the corresponding signal as an output. Any bit cleared in this register
configures the corresponding signal as an input. The software is responsible for ensuring that DDR bits are
not set on signals used for analog inputs. When the DDR bit is set, thereby selecting the signal for analog
conversion, the voltage sampled is that of the output digital driver as influenced by the load.
NOTE
Caution should be exercised when mixing digital and analog inputs. This
should be isolated as much as possible. Rise and fall times should be as large
as possible to minimize AC coupling effects.
There are two special cases to consider for the digital I/O port operation. When QACR0[EMUX] is set,
enabling external multiplexing, the data direction register settings are ignored for the bits corresponding
to PORTQA[2:0], which are the three multiplexed address (MA[2:0]) output signals. The MA[2:0] signals
are forced to be digital outputs, regardless of the data direction setting, and the multiplexed address outputs
are driven. The data returned during a port data register read is the value of the multiplexed address latches
which drive MA[2:0], regardless of the data direction setting.
13.3.5
Control Register 0 (QACR0)
Control Register 0 is used to define whether external multiplexing is enabled, assign external triggers to
the conversion queues and to sets up the QCLK prescaler parameter field. All of the implemented control
MULTIPLEXED ANALOG INPUTS:
ANz
ANy
ANx
ANw
Table 13-8. PORTQA, PORTQB Bit Descriptions
Bits
Name
Description
0:7
PQA[7:0]
Port A signals are referred to as PQA when used as an 8-bit input/output port. Port A can also
be used for analog inputs (AN[59:52]), and external multiplexer address outputs (MA[2:0]).
8:15
PQB[7:0]
Port B signals are referred to as PQB when used as an 8 input-only port. Port B can also be used
for non-multiplexed (AN[51:48]/AN[3:0]) and multiplexed (ANz, ANy, ANx, ANw) analog inputs.
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
Field DDQ
A7
DDQ
A6
DDQ
A5
DDQ
A4
DDQ
A3
DDQ
A2
DDQ
A1
DDQ
A0
—
SRESET
0000_0000_0000_0000
Addr
0x30 4808 (DDRQA_A); 0x30 4C08 (DDRQA_B)
Figure 13-8. Port A Data Direction Register (DDRQA)
Figure 13-7. Port
x
Data Register (PORTQA and PORTQB)
Summary of Contents for MPC561
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