QADC64E Legacy Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
13-76
Freescale Semiconductor
In addition to internal junction leakage, external leakage (e.g., if external clamping diodes are used) and
charge sharing effects with internal capacitors also contribute to the total leakage current.
illustrates the effect of different levels of total leakage on accuracy for different values of source
impedance. The error is listed in terms of 10-bit counts.
CAUTION
Leakage from the part below 200 nA is obtainable only within a limited
temperature range.
13.7.5.4
Accommodating Positive/Negative Stress Conditions
Positive or negative stress refers to conditions which exceed nominally defined operating limits. Examples
include applying a voltage exceeding the normal limit on an input (for example, voltages outside of the
suggested supply/reference ranges) or causing currents into or out of the signal which exceed normal
limits. QADC64E specific considerations are voltages greater than V
DDA
, V
RH
or less than V
SSA
applied to
an analog input which cause excessive currents into or out of the input. Refer to
to for more information on exact magnitudes.
Either stress condition can potentially disrupt conversion results on neighboring inputs. Parasitic devices,
associated with CMOS processes, can cause an immediate disruptive influence on neighboring signals.
Common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal
tied to substrate (V
SSI
/V
SSA
ground). Under stress conditions, current injected on an adjacent signal can
cause errors on the selected channel by developing a voltage drop across the selected channel’s
impedances.
shows an active parasitic bipolar NPN transistor when an input signal is subjected to negative
stress conditions.
shows positive stress conditions can activate a similar PNP transistor.
Figure 13-54. Input Signal Subjected to Negative Stress
Table 13-25. Error Resulting from Input Leakage (IOFF)
Source
Impedance
Leakage Value (10-bit Conversions)
100 nA
200 nA
500 nA
1000 nA
1 k
Ω
—
—
0.1 counts
0.2 counts
10 k
Ω
0.2 counts
0.4 counts
1 counts
2 counts
100 k
Ω
2 counts
4 count
10 counts
20 counts
QADC64E PAR
R
STRESS
R
SELECTED
Adjacent
10K
Signal Under
Parasitic
I
INJN
I
IN
+
Stress
V
STRESS
Device
signal
V
IN
AN
n
AN
n+1
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
Page 854: ...Time Processor Unit 3 MPC561 MPC563 Reference Manual Rev 1 2 19 24 Freescale Semiconductor...
Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
