QADC64E Enhanced Mode Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
14-11
attempts to write unimplemented data space, the QADC64E causes a bus error condition and no
data is written.
•
Attempts to read assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and no data
is returned.
•
Attempts to write assignable data space in the unrestricted access mode when the space is
programmed as supervisor space causes the bus master to assert a bus error condition and the
register is not written.
The bus master indicates the supervisor and user space access with the function code bits (FC[2:0]) on the
IMB3. For privilege violations, refer to
Chapter 9, “External Bus Interface
” to determine the consequence
of a bus error cycle termination.
The supervisor-only data space segment contains the QADC64E global registers, which include the
QADCMCR, QADCINT and QADCTEST. The supervisor/unrestricted space designation for the CCW
table, the result word table and the remaining QADC64E registers is programmable.
14.3.2
QADC64E Interrupt Register
QADCINT specifies the priority level of QADC64E interrupt requests. The interrupt level for queue 1 and
queue 2 may be different. The interrupt register is read/write accessible in supervisor data space only. The
implemented interrupt register fields can be read and written, reserved bits read zero and writes have no
effect. They are typically written once when the software initializes the QADC64E, and not changed
afterwards.
Table 14-6. QADC64E Bus Error Response
S/U
1
Mode
1
S/U = Supervisor/Unrestricted
SUPV Bit
Supervisor-Only
Register
Supervisor/
Unrestricted Register
Reserved/
Unimplemented
Register
U
0
QADC64E bus error
2
2
QADC64E bus error = Caused by QADC64E
Valid access
4
QADC64E bus error
2
U
1
Master bus error
3
3
Master bus error = Caused by bus master
4 Access to QADCTEST register will act as a reserved/unimplemented register unless in factory
test mode
Master bus error
3
Master bus error
3
S
0
Valid access
Valid access
QADC64E bus error
2
S
1
Valid access
Valid access
QADC64E bus error
2
Summary of Contents for MPC561
Page 84: ...MPC561 MPC563 Reference Manual Rev 1 2 lxxxiv Freescale Semiconductor...
Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
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Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...
