Queued Serial Multi-Channel Module
MPC561/MPC563 Reference Manual, Rev. 1.2
15-22
Freescale Semiconductor
15.6.2
QSPI RAM
The QSPI contains a 160-byte block of dual-ported static RAM that can be accessed by both the QSPI and
the CPU. Because of this dual access capability, up to two wait states may be inserted into CPU access
time if the QSPI is in operation.
The size and type of access of the QSPI RAM by the CPU affects the QSPI access time. The QSPI allows
byte, half-word, and word accesses. Only word accesses of the RAM by the CPU are coherent because
these accesses are an indivisible operation. If the CPU makes a coherent access of the QSPI RAM, the
QSPI cannot access the QSPI RAM until the CPU is finished. However, a word or misaligned word access
is not coherent because the CPU must break its access of the QSPI RAM into two parts, which allows the
QSPI to access the QSPI RAM between the two accesses by the CPU.
The RAM is divided into three segments: receive data RAM, transmit data RAM, and command data
RAM. Receive data is information received from a serial device external to the MCU. Transmit data is
information stored for transmission to an external device. Command data defines transfer parameters.
shows RAM organization.
Table 15-18. SPSR Bit Descriptions
Bits
Name
Description
0:7
SPCR3
See bit descriptions in
8
SPIF
QSPI finished flag. SPIF is set after execution of the command at the address in ENDQP in
SPCR2. If wraparound mode is enabled (WREN = 1), the SPIF is set, after completion of the
command defined by ENDQP, each time the QSPI cycles through the queue.
0 QSPI is not finished
1 QSPI is finished
9
MODF
Mode fault flag. The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the
SS input pin is negated by an external driver. Refer to
” for more
information.
0 Normal operation
1 Another SPI node requested to become the network SPI master while the QSPI was enabled
in master mode (SS input taken low).
10
HALTA
Halt acknowledge flag. HALTA is set when the QSPI halts in response to setting the HALT bit in
SPCR3. HALTA is also set when the IMB3 FREEZE signal is asserted, provided the FRZ1 bit in
the QSMCMMCR is set. To prevent undefined operation, no modification should be made to any
QSPI control registers or RAM while the QSPI is halted.
If HMIE in SPCR3 is set the QSPI sends interrupt requests to the CPU when HALTA is asserted.
0 QSPI is not halted.
1 QSPI is halted
11:15
CPTQP
Completed queue pointer. CPTQP points to the last command executed. It is updated when the
current command is complete. When the first command in a queue is executing, CPTQP contains
either the reset value 0x0 or a pointer to the last command completed in the previous queue.
If the QSPI is halted, CPTQP may be used to determine which commands have not been
executed. The CPTQP may also be used to determine which locations in the receive data
segment of the QSPI RAM contain valid received data.
Summary of Contents for MPC561
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Page 144: ...Signal Descriptions MPC561 MPC563 Reference Manual Rev 1 2 2 46 Freescale Semiconductor...
Page 206: ...Central Processing Unit MPC561 MPC563 Reference Manual Rev 1 2 3 62 Freescale Semiconductor...
Page 302: ...Reset MPC561 MPC563 Reference Manual Rev 1 2 7 14 Freescale Semiconductor...
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Page 968: ...Development Support MPC561 MPC563 Reference Manual Rev 1 2 23 54 Freescale Semiconductor...
Page 1144: ...Internal Memory Map MPC561 MPC563 Reference Manual Rev 1 2 B 34 Freescale Semiconductor...
Page 1212: ...TPU3 ROM Functions MPC561 MPC563 Reference Manual Rev 1 2 D 60 Freescale Semiconductor...
Page 1216: ...Memory Access Timing MPC561 MPC563 Reference Manual Rev 1 2 E 4 Freescale Semiconductor...